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| datasheet r01ds0193ej0200 rev.2.00 sep 06, 2013 page 1 of 106 r01ds0193ej0200 rev.2.00 sep 06, 2013 rl78/g12 renesas mcu true low power platform (as low as 63 a/mhz), 1.8v to 5.5v operation, 2 to 16 kbyte flash, 31 dmips at 24mhz, for general purpose applications 1. outline 1.1 features ultra-low power technology ? 1.8 v to 5.5 v operation from a single supply ? stop (ram retained): 0.23 a, (lvd enabled): 0.31 a ? snooze: 0.7 ma (uart), 1.20 ma (adc) ? operating: 63 a /mhz 16-bit rl78 cpu core ? delivers 31 dmips at maximum operating frequency of 24 mhz ? instruction execution: 86 % of instructions can be executed in 1 to 2 clock cycles ? cisc architecture (harvard) with 3-stage pipeline ? multiply signed & unsigned: 16 x 16 to 32-bit result in 1 clock cycle ? mac: 16 x 16 to 32-bit result in 2 clock cycles ? 16-bit barrel shifter for shi ft & rotate in 1 clock cycle ? 1-wire on-chip debug function main flash memory ? density: 2 kb to 16 kb ? block size: 1 kb ? on-chip single voltage flash memory with protection from block erase/writing data flash memory ? data flash with background operation ? data flash size: 2 kb size options ? erase cycles: 1 million (typ.) ? erase/programming voltage: 1.8 v to 5.5 v ram ? 256 b to 1.5 kb size options ? supports operands or instructions ? back-up retention in all modes high-speed oscillator oscillator ? 24mhz with +/- 1% accuracy over voltage (1.8 v to 5.5 v) and temperature (-20 c to 85 c) ? pre-configured settings: 24 mhz, 16 mhz, 12 mhz, 8 mhz, 6 mhz, 4 mhz, 3 mhz, 2 mhz, and 1 mhz reset and supply management ? power-on reset (por) monitor/generator ? low voltage detection (lvd) with 12 setting options (interrupt and/or reset function) data memory access (dma) controller ? up to 2 fully programmable channels ? transfer unit: 8- or 16-bit multiple communication interfaces ? up to 3 x i 2 c master ? up to 1 x i 2 c multi-master ? up to 3 x csi/spi (7-, 8-bit) ? up to 3 x uart (7-, 8-, 9-bit) extended-function timers ? multi-function 16-bit timers: up to 8 channels ? interval timer: 12-bit, 1 channel ? 15 khz watchdog timer : 1 channel (window function) rich analog ? adc: up to 11 channels, 10-bit resolution, 2.1 s conversion time ? supports 1.8 v to 5.5 v ? internal voltage reference (1.45 v) ? on-chip temperature sensor safety features (iec or ul 60730 compliance) ? flash memory crc calculation ? ram parity error check ? ram write protection ? sfr write protection ? illegal memory access detection ? clock stop/ frequency detection ? adc self-test general purpose i/o ? 5 v tolerant, high-current (up to 20 ma per pin) ? open-drain, internal pull-up support operating ambient temperature ? standard: ?40 c to +85 c ? extended: ?40 c to +105 c package type and pin count ? qfn: 24 ? ssop: 20, 30 * there is difference in specifications between every product. please refer to specification for details. rl78/g12 1. outline r01ds0193ej0200 rev.2.00 sep 06, 2013 page 2 of 106 ? rom, ram capacities code flash data flash ram 20 pins 24 pins 30 pins 16 kb 2 kb 2 kb ? ? r5f102aa ? ? ? r5f103aa 2 kb 1.5 kb r5f1026a note 1 r5f1027a note 1 ? ? r5f1036a note 1 r5f1037a note 1 ? 12 kb 2kb 1 kb r5f10269 note 1 r5f10279 note 1 r5f102a9 ? r5f10369 note 1 r5f10379 note 1 r5f103a9 8 kb 2 kb 768 b r5f10268 note 1 r5f10278 note 1 r5f102a8 ? r5f10368 note 1 r5f10378 note 1 r5f103a8 4 kb 2kb 512 b r5f10267 r5f10277 r5f102a7 ? r5f10367 r5f10377 r5f103a7 2 kb 2 kb 256 b r5f10266 note 2 ? ? ? r5f10366 note 2 ? ? notes 1. this is 640 bytes when the self-programming function or data flash function is used. (for details, see chapter 3 cpu architecture in the rl78/g12 user?s manual hardware .) 2. the self-programming function cannot be used for r5f10266 and r5f10366. caution when the flash memory is rewritten via a user program, the code flash area and ram area are used because each library is used. when using the library, refer to rl78 family flash self programming library type01 user's manual and rl78 family data flash library type04 user's manual. rl78/g12 1. outline r01ds0193ej0200 rev.2.00 sep 06, 2013 page 3 of 106 1.2 list of part numbers figure 1-1. part number, memory size, and package of rl78/g12 part no. r 5 f 1 0 2 a a a x x x s p #v0 package type: rom number (omitted with blank products) rom capacity: rl78/g12 group renesas mcu renesas semiconductor product sp : lssop, 0.65 mm pitch na : hwqfn, 0.50 mm pitch #u0 : tray (hwqfn) #v0 : tray (lssop30), tube (lssop20) #w0: embossed tape (hwqfn) #x0 : embossed tape (lssop30, lssop20) 6 : 2 kb 7 : 4 kb 8 : 8 kb 9 : 12 kb a : 16 kb pin count: 6 : 20-pin 7 : 24-pin a : 30-pin classification: a : consumer applications, t a = -40?c to +85?c d : industrial applications, t a = -40?c to +85?c g : industrial applications, t a = -40?c to +105?c memory type: f : flash memory packaging specifications: 102 note 1 103 notes 1, 2 notes 1. for details about the differences between the r5f1 02 products and the r5f103 products of rl78/g12, see 1.3 differences between the r5f 102 products and the r5f103 products . 2. products only for "a: consumer applications (t a = -40 to +85 c)" and "d: industrial applications (t a = -40 to +85 c)" rl78/g12 1. outline r01ds0193ej0200 rev.2.00 sep 06, 2013 page 4 of 106 table 1-1. list of ordering part numbers pin count package data flash fields of application part number 20 pins 20-pin plastic lssop (4.4 6.5 mm, 0.65 mm pitch) mounted a r5f1026aasp#v0, r5f10269asp#v0, r5f10268asp#v0, r5f10267asp#v0, r5f10266asp#v0 r5f1026aasp#x0, r5f10269asp#x0, r5f10268asp#x0, r5f10267asp#x0, r5f10266asp#x0 d r5f1026adsp#v0, r5f10269dsp#v0, r5f10268dsp#v0, r5f10267dsp#v0, r5f10266dsp#v0 r5f1026adsp#x0, r5f10269dsp#x0, r5f10268dsp#x0, r5f10267dsp#x0, r5f10266dsp#x0 g r5f1026agsp#v0, r5f10269gsp#v0, r5f10268gsp#v0, r5f10267gsp#v0, r5f10266gsp#v0 r5f1026agsp#x0, r5f10269gsp#x0, r5f10268gsp#x0, r5f10267gsp#x0, r5f10266gsp#x0 not mounted a r5f1036aasp#v0, r5f10369asp#v0, r5f10368asp#v0, r5f10367asp#v0, r5f10366asp#v0 r5f1036aasp#x0, r5f10369asp#x0, r5f10368asp#x0, r5f10367asp#x0, r5f10366asp#x0 d r5f1036adsp#v0, r5f10369dsp#v0, r5f10368dsp#v0, r5f10367dsp#v0, r5f10366dsp#v0 r5f1036adsp#x0, r5f10369dsp#x0, r5f10368dsp#x0, r5f10367dsp#x0, r5f10366dsp#x0 24 pins 24-pin plastic hwqfn (4 4 mm, 0.5 mm pitch) mounted a r5f1027aana#u0, r5f10279ana#u0, r5f10278ana#u0, r5f10277ana#u0 r5f1027aana#w0, r5f10279ana#w0, r5f10278ana#w0, r5f10277ana#w0 d r5f1027adna#u0, r5f10279dna#u0, r5f10278dna#u0, r5f10277dna#u0 r5f1027adna#w0, r5f10279dna#w0, r5f10278dna#w0, r5f10277dna#w0 g r5f1027agna#u0, r5f10279gna#u0, r5f10278gna#u0, r5f10277gna#u0 r5f1027agna#w0, r5f10279gna#w0, r5f10278gna#w0, r5f10277gna#w0 not mounted a r5f1037aana#v0, r5f10379ana#v0, r5f10378ana#v0, r5f10377ana#v0 r5f1037aana#x0, r5f10379ana#x0, r5f10378ana#x0, r5f10377ana#x0 d r5f1037adna#v0, r5f10379dna#v0, r5f10378dna#v0, r5f10377dna#v0 r5f1037adna#x0, r5f10379dna#x0, r5f10378dna#x0, r5f10377dna#x0 30 pins 30-pin plastic lssop (7.62 mm (300), 0.65 mm pitch ) mounted a r5f102aaasp#v0, r5f102a9asp#v0, r5f102a8asp#v0, r5f102a7asp#v0 r5f102aaasp#x0, r5f102a9asp#x0, r5f102a8asp#x0, r5f102a7asp#x0 d r5f102aadsp#v0, r5f102a9dsp#v0, r5f102a8dsp#v0, r5f102a7dsp#v0 r5f102aadsp#x0, r5f102a9dsp#x0, r5f102a8dsp#x0, r5f102a7dsp#x0 g r5f102aagsp#v0, r5f102a9gsp#v0, r5f102a8gsp#v0, r5f102a7gsp#v0 r5f102aagsp#x0, r5f102a9gsp#x0, r5f102a8gsp#x0, r5f102a7gsp#x0 not mounted a r5f103aaasp#v0, r5f103a9asp#v0, r5f103a8asp#v0, r5f103a7asp#v0 r5f103aaasp#x0, r5f103a9asp#x0, r5f103a8asp#x0, r5f103a7asp#x0 d r5f103aadsp#v0, r5f103a9dsp#v0, r5f103a8dsp#v0, r5f103a7dsp#v0 r5f103aadsp#x0, r5f103a9dsp#x0, r5f103a8dsp#x0, r5f103a7dsp#x0 note for fields of application, see figure 1-1. part number, memory size, and package of rl78/g12 . caution the ordering part numbers represent the numbers at the time of publication. for the latest ordering part numbers, refer to the target product page of the renesas electronics website. rl78/g12 1. outline r01ds0193ej0200 rev.2.00 sep 06, 2013 page 5 of 106 1.3 differences between the r5f102 products and the r5f103 products the following are differences between the r5f102 products and the r5f103 products. ? whether the data flash memory is mounted or not ? high-speed on-chip oscillator oscillation frequency accuracy ? number of channels in serial interface ? whether the dma function is mounted or not ? whether a part of the safety functions are mounted or not 1.3.1 data flash the data flash memory of 2 kb is mounted on the r5f102 products, but not on the r5f103 products. product data flash r5f102 products r5f1026a, r5f1027a, r5f102aa, r5f10269, r5f10279, r5f102a9, r5f10268, r5f10278, r5f102a8, r5f10267, r5f10277, r5f102a7, r5f10266 note 2kb r5f103 products r5f1036a, r5f1037a, r5f103aa, r5f10369, r5f10379, r5f103a9, r5f10368, r5f10378 r5f103a8, r5f10367, r5f10377, r5f103a7, r5f10366 not mounted note the ram in the r5f10266 has capacity as small as 256 bytes. depending on the customer's program specification, the sta ck area to execute the data flash library may not be kept and data may not be written to or erased from the data flash memory. caution when the flash memory is rewritten via a user program, the code flash area and ram area are used because each library is used. when using the library, refer to rl78 family flash self programming library type01 user's manual and rl78 family data flash library type04 user's manual. rl78/g12 1. outline r01ds0193ej0200 rev.2.00 sep 06, 2013 page 6 of 106 1.3.2 on-chip oscillator characteristics (1) high-speed on-chip oscillator oscillation frequency of the r5f102 products oscillator condition min max unit high-speed on-chip oscillator oscillation frequency accuracy t a = -20 to +85 c -1.0 +1.0 % t a = -40 to -20 c -1.5 +1.5 t a = +85 to +105 c -2.0 +2.0 (2) high-speed on-chip oscillator oscillation frequency of the r5f103 products oscillator condition min max unit high-speed on-chip oscillator oscillation frequency accuracy t a = -40 to + 85 c -5.0 +5.0 % 1.3.3 peripheral functions the following are differences in peripheral functions between the r5f102 products and the r5f103 products. rl78/g12 r5f102 product r5f103 product 20, 24 pin product 30 pin product 20, 24 pin product 30 pin product serial interface uart 1 channel 3 channels 1 channel csi 2 channels 3 channels 1 channel simplified i 2 c 2 channels 3 channels none dma function 2 channels none safety function crc operation yes none ram guard yes none sfr guard yes none rl78/g12 1. outline r01ds0193ej0200 rev.2.00 sep 06, 2013 page 7 of 106 1.4 pin configuration (top view) 1.4.1 20-pin products ? 20-pin plastic lssop (4.4 6.5 mm, 0.65 mm pitch) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 p21/ani1/av refm p22/ani2 p23/ani3 p10/ani16/pclbuz0/sck00/scl00 p11/ani17/si00/rxd0/sda00 /toolrxd p12/ani18/so00/txd0/tooltxd p13/ani19/ti00/to00/intp2 p14/ani20/ti01/to01/intp3 p61/kr5/sdaa0/(rxd0) p60/kr4/scla0/(txd0) p20/ani0/av refp p40/kr0/tool0 p137/intp0 p122/kr2/x2/exclk/(ti02)/(intp2) p121/kr3/x1/(ti03)/(intp3) v ss v dd p42/ani21/sck01 /scl01 note note /ti03/to03 p41/ani22/so01 /sda01 note note /ti02/to02/intp1 p125/kr1/si01 / reset note note note note provided only in the r5f102 products. remarks 1. for pin identification, see 1.5 pin identification . 2. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). see figure 4-8 format of peripheral i/o redi rection register (pior) in the rl78/g12 user?s manual hardware. . rl78/g12 1. outline r01ds0193ej0200 rev.2.00 sep 06, 2013 page 8 of 106 1.4.2 24-pin products ? 24-pin plastic hwqfn (4 4 mm, 0.5 mm pitch) 1 2 3 4 5 6 12 11 10 9 8 7 18 17 16 15 14 13 19 20 21 22 23 24 p61/kr5/sdaa00/(rxd0) p60/kr4/scla0/(txd0) p03/kr9 p02/kr8/(sck01) note /(scl01) note p01/kr7/(so01) note /(sda01) note p00/kr6/(si01) note p22/ani2 p21/ani1/av refm p20/ani0/av refp p42/ani21/sck01 note /scl01 note /ti03/to03 p41/ani22/so01 note /sda01 note /ti02/to02/intp1 p40/kr0/tool0 index mark exposed die pad v dd v ss p122/kr2/x2/exclk/(ti02)/(intp2) p121/kr3/x1/(ti03)/(intp3) p137/intp0 p125/kr1/si01 note /reset p14/ano20/ti01/ontp3 p13/ano19/ti00/ontp2 p11/ani17/si00/sda00 note /toolrxd p12/ani18/so00/txd0/tooltxd p10/ani16/pclbuz0/sck00/scl00 note p23/ani3 note provided only in the r5f102 products. remarks 1. for pin identification, see 1.5 pin identification . 2. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). see figure 4-8 format of peripheral i/o redire ction register (pior) in the rl78/g12 user?s manual hardware . 3. it is recommended to connect an exposed die pad to vss. rl78/g12 1. outline r01ds0193ej0200 rev.2.00 sep 06, 2013 page 9 of 106 1.4.3 30-pin products ? 30-pin plastic lssop (7.62 mm (300), 0.65 mm pitch) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 p20/ani0/av refp p01/ani16/to00/rxd1 note p00/ani17/to00/txd1 note p120/ani19 p40/tool0 reset p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd p60/scla0 p61/sdaa0 p31/ti03/to03/intp4/pclbuz0 p21/ani1/av refm p22/ani2 p23/ani3 p147/ani18 p10/sck00/scl00 note /(ti07/to07) p11/si00/rxd0/toolrxd/sda00 note /(ti06/to06) p13/txd2 note /so20 note /(sdaa0) note /(ti04/to04) p14/rxd2 note /si20 note /sda20 note /(scla0)/(ti03/to03) p15/pclbuz1/sck20 note /scl20 note /(ti02/to02) p12/so00/txd0/tooltxd/(ti05/to05) p16/ti01/to01/intp5/(rxd0) p17/ti02/to02/(txd0) p30/intp3/sck11 note /scl11 note p51/intp2/so11 note /sda11 note p50/intp1/si11 note note provided only in the r5f102 products. caution connect the regc pin to v ss via capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.5 pin identification . 2. functions in parentheses in the above figure can be assigned via setting s in the peripheral i/o redirection register (pior). see figure 4-8 format of peripheral i/o redirection register (pior) in the rl78/g12 user?s manual hardware. rl78/g12 1. outline r01ds0193ej0200 rev.2.00 sep 06, 2013 page 10 of 106 1.5 pin identification a ni0 to ani3, a ni16 to ani22: a nalog input regc: reset: regulator capacitance reset a v refm : a nalog reference voltage minus rxd0 to rxd2: sck00, sck01, sck11, receive data a v refp : a nalog reference voltage plus exclk: external clock input (main system clock) sck20: scl00, scl01, serial clock input/output intp0 to intp5 interrupt request from peripheral scl11, scl20, scla0: sda00, sda01, sda11, serial clock input/output kr0 to kr9: key return p00 to p03: port 0 sda20, sdaa0: serial data input/output p10 to p17: port 1 si00, si01, si11, si20: serial data input p20 to p23: port 2 so00, so01, so11, p30 to p31: port 3 so20: serial data output p40 to p42: port 4 ti00 to ti07: timer input p50, p51: port 5 to00 to to07: timer output p60, p61: port 6 tool0: data input/output for tool p120 to p122, p125: port 12 toolrxd, tooltxd: data input/output for external device p137: port 13 p147: port 14 txd0 to txd2: transmit data pclbuz0, pclbuz1: programmable clock output/ buzzer output v dd : power supply v ss : ground x1, x2: crystal oscillator (main system clock) rl78/g12 1. outline r01ds0193ej0200 rev.2.00 sep 06, 2013 page 11 of 106 1.6 block diagram 1.6.1 20-pin products port 1 p10 to p14 port 2 p20 to p23 4 port 4 p40 to p42 2 port 6 port 12 5 crc note pclbuz0 p60, p61 p121, p122, p125 reset low speed on-chip oscillator 15 khz 9 6 4 kr0 to kr5 intp0 to intp3 ani2, ani3, ani16 to ani22 ani0/av refp ani1/av refm port 13 p137 3 3 multiplier & divider multiply- accumulator on-chip debug bcd adjustment iica0 tool0 scla0 sdaa0 power-on reset/voltage detector clock generator + reset generator high-speed on-chip oscillator 1 to 24 mhz tool txd tool rxd rl78 cpu core buzzer/clock output control key return 6ch interrupt control 4ch window watchdog timer 12-bit intervaltimer 10-bit a/d converter 11ch ram 1.5 kb interrupt control dma note 2ch code flash: 16 kb data flash: 2 kb note sau0 (2ch) uart0 csi00 csi01 note iic00 note iic01 note ti00/to00 tau0 (4ch) ch00 ch01 ch02 ch03 ti01/to01 ti02/to02 ti03/to03 rxd0 txd0 sck00 si00 so00 sck01 si01 so01 scl00 sda00 scl01 sda01 main osc 1 to 20 mhz v dd v ss x1 x2/exclk note provided only in the r5f102 products. rl78/g12 1. outline r01ds0193ej0200 rev.2.00 sep 06, 2013 page 12 of 106 1.6.2 24-pin products 4 2 5 9 10 4 4 3 3 code flash: 16 kb data flash: 2 kb note tau0 (4ch) ch01 ch00 interrupt control rl78 cpu core low speed on-chip oscillator 15 khz dma note 2ch ram 1.5 kb poer-on reset/voltage detector high-speed on-chip oscillator 1 to 24 mhz clock generator + reset generator ch02 ch03 uart0 sau0 (2ch) csi00 iica0 on-chip debug multiplier & divider/ multiply- accumulator bcd adjustment csi01 note iic00 note iic01 note ti00/to00 ti01/to01 ti02/to02 ti03/to03 rxd0 txd0 sck00 si00 so00 sck01 si01 so01 scl00 sda00 scl01 sda01 scla0 sdaa0 tool0 v dd v ss port 0 p00 to p03 p10 to p14 p20 to p23 p40 to p42 p60, p61 p137 pclbuz0 kr0 to kr9 intp0 to intp3 ani2, ani3, ani16 to ani22 10-bit a/d converter 11ch 12-bit interval timer window watchdog timer crc note ani0/av refp ani1/av refm p121, p122, 125 port 1 port 2 port 4 port 6 port 12 key return 10ch interrupt control 4ch buzzer/clock output control port 13 reset main osc 1to 20 mhz x1 x2/exclk tool txd tool rxd iica0 note provided only in the r5f102 products. rl78/g12 1. outline r01ds0193ej0200 rev.2.00 sep 06, 2013 page 13 of 106 1.6.3 30-pin products 4 2 8 6 2 6 2 2 2 2 voltage regulator regc ani0/av refp ani1/av refm ani2, ani3, ani16 to ani19 tau (8ch) ti00 to00 rxd0 txd0 rxd2 txd2 tool0 iica0 on-chip debug bcd adjustment scla0 sdaa0 scl20 sda20 sck20 si20 so20 scl00 sda00 scl11 sda11 rxd1 txd1 sck00 si00 so00 sck11 si11 so11 ti01/to01 ti02/to02 ti03/to03 (ti04/to04) (ti05/to05) (ti06/to06) (ti07/to07) ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 sau0 (4ch) sau0 (2ch) note uart2 csi20 iic20 uart0 uart1 note csi00 csi11 note iic00 note iic11 note low speed on-chip oscillator 15 khz p00, p01 p10 to p17 p20 to p23 p30, p31 p40 p50, p51 p60, p61 p120 p121, p122 p137 p147 pclbuz0, pclbuz1 intp0 to intp5 port 1 port 0 port 2 port 3 port 4 port 5 port 6 port 12 port 13 port 14 multiplier & divider/ multiply- accumulator code flash: 16 kb data flash: 2 kb note interrupt control rl78 cpu core dma note 2ch ram 2 kb poer-on reset/voltage detector high-speed on-chip oscillator 1 to 24 mhz clock generator + reset generator v dd v ss reset main osc 1 to 20 mhz x1 x2/exclk tool txd tool rxd 10-bit a/d converter 8ch 12-bit interval timer window watchdog timer crc note interrupt control 6ch buzzer/clock output control note provided only in the r5f102 products. remark functions in parentheses in the above figure can be a ssigned via settings in the peripheral i/o redirection register (pior). see figure 4-8 format of peripheral i/o redirection register (pior) in the rl78/g12 user?s manual hardware . rl78/g12 1. outline r01ds0193ej0200 rev.2.00 sep 06, 2013 page 14 of 106 1.7 outline of functions this outline describes the function at the time when pe ripheral i/o redirection regist er (pior) is set to 00h. (1/2) item 20-pin 24-pin 30-pin r5f1026x r5f1036x r5f1027x r5f1037x r5f102ax r5f103ax code flash memory 2 to 16 kb note 1 4 to 16 kb data flash memory 2 kb ? 2 kb ? 2 kb ? ram 256 b to 1.5 kb 512 b to 1.5 kb 512 b to 2kb address space 1 mb main system clock high-speed system clock x1, x2 (crystal/ceramic) oscillation, exte rnal main system clock input (exclk) 1 to 20 mhz: v dd = 2.7 to 5.5 v, 1 to 8 mhz: v dd = 1.8 to 5.5 v high-speed on-chip oscillator clock hs (high-speed main) mode : 1 to 24 mhz (v dd = 2.7 to 5.5 v), 1 to 16 mhz (v dd = 2.4 to 5.5 v), ls (low-speed main) mode : 1 to 8 mhz (v dd = 1.8 to 5.5 v) low-speed on-chip oscillator clock 15 khz (typ) general-purpose register (8-bit register 8) 4 banks minimum instruction execution time 0.04167 s (high-speed on-chip oscillator clock: f ih = 24 mhz operation) 0.05 s (high-speed system clock: f mx = 20 mhz operation) instruction set ? data transfer (8/16 bits) ? adder and subtractor/logical operation (8/16 bits) ? multiplication (8 bits 8 bits) ? rotate, barrel shift, and bit manipulation (s et, reset, test, and boolean operation), etc. i/o port total 18 22 26 cmos i/o 12 (n-ch o.d. i/o [v dd withstand voltage]: 4) 16 (n-ch o.d. i/o [v dd withstand voltage]: 5) 21 (n-ch o.d. i/o [v dd withstand voltage]: 9) cmos input 4 4 3 n-ch open-drain i/o (6 v tolerance) 2 timer 16-bit timer 4 channels 8 channels watchdog timer 1 channel 12-bit interval timer 1 channel timer output 4 channels (pwm outputs: 3 note 3 ) 8 channels (pwm outputs: 7 note 3 ) note 2 notes 1. the self-programming function cannot be used in the r5f10266 and r5f10366. 2. the maximum number of channels when pior0 is set to 1. 3. the number of pwm outputs varies depending on the setting of channels in use (the number of masters and slaves). (see 6.9.3 operation as multiple pwm output function in the rl78/g12 user?s manual hardware .) caution when the flash memory is rewritten via a user program, the code flash area and ram area are used because each library is used. when using the library, refer to rl78 family flash self programming library type01 user's manual and rl78 family data flash library type04 user's manual. rl78/g12 1. outline r01ds0193ej0200 rev.2.00 sep 06, 2013 page 15 of 106 (2/2) item 20-pin 24-pin 30-pin r5f1026x r5f1036x r5f1027x r5f1037x r5f102ax r5f103ax clock output/buzzer output 1 2 2.44 khz to 10 mhz: (peripheral hardware clock: f main = 20 mhz operation) 8/10-bit resolution a/d c onverter 11 channels 8 channels serial interface [r5f1026x (20-pin), r5f1027x (24-pin)] ? csi: 2 channels/simplified i 2 c: 2 channels/uart: 1 channel [r5f102ax (30-pin)] ? csi: 1 channel/simplified i 2 c: 1 channel/uart: 1 channel ? csi: 1 channel/simplified i 2 c: 1 channel/uart: 1 channel ? csi: 1 channel/simplified i 2 c: 1 channel/uart: 1 channel [r5f1036x (20-pin), r5f1037x (24-pin)] ? csi: 1 channel/simplified i 2 c: 0 channel/uart: 1 channel [r5f103ax (30-pin)] ? csi: 1 channel/simplified i 2 c: 0 channel/uart: 1 channel i 2 c bus 1 channel multiplier and divider/multiply- accumulator ? 16 bits 16 bits = 32 bits (unsigned or signed) ? 32 bits 32 bits = 32 bits (unsigned) ? 16 bits 16 bits + 32 bits = 32 bits (unsigned or signed) dma controller 2 channels ? 2 channels ? 2 channels ? vectored interrupt sources internal 18 16 18 16 26 19 external 5 6 key interrupt 6 10 ? reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-reset ? internal reset by voltage detector ? internal reset by illegal instruction execution note ? internal reset by ram parity error ? internal reset by illegal-memory access power-on-reset circuit ? power-on-reset: 1.51 v (typ) ? power-down-reset: 1.50 v (typ) voltage detector ? rising edge : 1.88 to 4.06 v (12 stages) ? falling edge : 1.84 to 3.98 v (12 stages) on-chip debug function provided power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = ? 40 to +85 c (a: consumer applications, d: industrial applications), t a = ? 40 to +105 c (g: industrial applications) note the illegal instruction is generated wh en instruction code ffh is executed. reset by the illegal instruction execution not issued by em ulation with the in-circuit emulator or on-chip debug emulator. rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 16 of 106 2. electrical specifications (a, d: t a = ? 40 to +85 c) this chapter describes the electrical specifications for the products "a: consumer applications (t a = -40 to +85 c)" and "d: industrial applications (t a = -40 to +85 c)". cautions 1. the rl78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug func tion in products designa ted for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability theref ore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. 2. the pins mounted depend on the product. refer to 2.1 port functi ons to 2.2.1 functions for each product in the rl78/g12 user?s manual hardware. rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 17 of 106 2.1 absolute maximum ratings absolute maximum ratings (t a = 25 c) parameter symbols conditions ratings unit supply voltage v dd ? 0.5 to + 6.5 v regc terminal input voltage note1 v iregc regc ? 0.3 to +2.8 and ?0.3 to v dd + 0.3 note 2 v input voltage v i1 other than p60, p61 ?0.3 to v dd + 0.3 note 3 v v i2 p60, p61 (n-ch open drain) ? 0.3 to 6.5 v output voltage v o ?0.3 to v dd + 0.3 note 3 v analog input voltage v ai 20-, 24-pin products: ani0 to ani3, ani16 to ani22 30-pin products: ani0 to ani3, ani16 to ani19 ?0.3 to v dd + 0.3 and ?0.3 to av ref(+) +0.3 notes 3, 4 v output current, high i oh1 per pin other than p20 to p23 ?40 ma total of all pins all the terminals other than p20 to p23 ? 170 ma 20-, 24-pin products: p40 to p42 30-pin products: p00, p01, p40, p120 ?70 ma 20-, 24-pin products: p00 to p03 note 5 , p10 to p14 30-pin products: p10 to p17, p30, p31, p50, p51, p147 ? 100 ma i oh2 per pin p20 to p23 ? 0.5 ma total of all pins ?2 ma output current, low i ol1 per pin other than p20 to p23 40 ma total of all pins all the terminals other than p20 to p23 170 ma 20-, 24-pin products: p40 to p42 30-pin products: p00, p01, p40, p120 70 ma 20-, 24-pin products: p00 to p03 note 5 , p10 to p14, p60, p61 30-pin products: p10 to p17, p30, p31, p50, p51, p60, p61, p147 100 ma i ol2 per pin p20 to p23 1 ma total of all pins 5 ma operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 65 to +150 c notes 1. 30-pin product only. 2. connect the regc pin to v ss via a capacitor (0.47 to 1 f). this value determines the absolute maximum rating of the regc pin. do not use it with voltage applied. 3. must be 6.5 v or lower. 4. do not exceed av ref (+) + 0.3 v in case of a/d conversion target pin . 5. 24-pin products only. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings ar e rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remarks 1. unless specified otherwise, the characteristics of alter nate-function pins are the sa me as those of the port pins. 2. av ref (+): + side reference voltage of the a/d converter. 3. v ss : reference voltage rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 18 of 106 2.2 oscillator characteristics 2.2.1 x1 oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd v dd 5.5 v, v ss = 0 v) parameter resonator conditions min. typ. max. unit x1 clock oscillation frequency (f x ) note ceramic resonator / crystal oscillator 2.7 v v dd 5.5 v 1.0 20.0 mhz 1.8 v v dd < 2.7 v 1.0 8.0 note indicates only permissible oscillator frequency ranges. re fer to ac characteristics for instruction execution time. request evaluation by the manufacturer of the oscill ator circuit mounted on a board to check the oscillator characteristics. caution since the cpu is started by the high-speed on-chip o scillator clock after a r eset release, check the x1 clock oscillation stabilization ti me using the oscillation stabilizati on time counter status register (ostc) by the user. determine the oscillation st abilization time of the ostc register and the oscillation stabilization time select register (osts) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. remark when using the x1 oscillator, refer to 5.4 system clock oscillator in the rl78/g12 user?s manual hardware. 2.2.2 on-chip oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) oscillators parameters conditions min. typ. max. unit high-speed on-chip oscillator clock frequency notes 1, 2 f ih 1 24 mhz high-speed on-chip oscillator clock frequency accuracy r5f102 products t a = ? 20 to +85 c-1.0 +1.0 % t a = ? 40 to ?20 c-1.5 +1.5 % r5f103 products -5.0 +5.0 % low-speed on-chip oscillator clock frequency f il 15 khz low-speed on-chip oscillator clock frequency accuracy -15 +15 % notes 1. high-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000c2h) and bits 0 to 2 of hocodiv register. 2. this only indicates the oscillator characteristics. refe r to ac characteristics for instruction execution time. rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 19 of 106 2.3 dc characteristics 2.3.1 pin characteristics (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) (1/4) parameter symbol conditions min. typ. max. unit output current, high note 1 i oh1 20-, 24-pin products: per pin for p00 to p03 note 4 , p10 to p14, p40 to p42 30-pin products: per pin for p00, p01, p10 to p17, p30, p31, p40, p50, p51, p120, p147 ?10.0 note 2 ma 20-, 24-pin products: total of p40 to p42 30-pin products: total of p00, p01, p40, p120 (when duty 70% note 3 ) 4.0 v v dd 5.5 v ? 30.0 ma 2.7 v v dd < 4.0 v ? 6.0 ma 1.8 v v dd < 2.7 v ? 4.5 ma 20-, 24-pin products: total of p00 to p03 note 4 , p10 to p14 30-pin products: total of p10 to p17, p30, p31, p50, p51, p147 (when duty 70% note 3 ) 4.0 v v dd 5.5 v ? 80.0 ma 2.7 v v dd < 4.0 v ? 18.0 ma 1.8 v v dd < 2.7 v ? 10.0 ma total of all pins (when duty 70% note 3 ) ? 100 ma i oh2 per pin for p20 to p23 ? 0.1 ma total of all pins ? 0.4 ma notes 1 . value of current at which the device operatio n is guaranteed even if the cu rrent flows from the v dd pin to an output pin. 2. however, do not exceed the total current value. 3. the output current value under conditions where the duty factor 70%. if duty factor > 70%: the output current value can be calculated with the following expression (where n represents the duty factor as a percentage). ? total output current of pins = (i oh 0.7)/(n 0.01) rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 20 of 106 (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) (2/4) parameter symbol conditions min. typ. max. unit output current, low note 1 i ol1 20-, 24-pin products: per pin for p00 to p03 note 4 , p10 to p14, p40 to p42 30-pin products: per pin for p00, p01, p10 to p17, p30, p31, p40, p50, p51, p120, p147 20.0 note 2 ma per pin for p60, p61 15.0 note 2 ma 20-, 24-pin products: total of p40 to p42 30-pin products: total of p00, p01, p40, p120 (when duty 70% note 3 ) 4.0 v v dd 5.5 v 60.0 ma 2.7 v v dd < 4.0 v 9.0 ma 1.8 v v dd < 2.7 v 1.8 ma 20-, 24-pin products: total of p00 to p03 note 4 , p10 to p14, p60, p61 30-pin products: total of p10 to p17, p30, p31, p50, p51, p60, p61, p147 (when duty 70% note 3 ) 4.0 v v dd 5.5 v 80.0 ma 2.7 v v dd < 4.0 v 27.0 ma 1.8 v v dd < 2.7 v 5.4 ma total of all pins (when duty 70% note 3 ) 140 ma i ol2 per pin for p20 to p23 0.4 ma total of all pins 1.6 ma notes 1 . value of current at which the devic e operation is guaranteed even if the current flow s from an output pin to the v ss pin. 2. however, do not exceed the total current value. 3. the output current value under conditions where the duty factor 70%. if duty factor > 70%: the output current value can be calculated with the following expression (where n represents the duty factor as a percentage). ? total output current of pins = (i ol 0.7)/(n 0.01) rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 21 of 106 (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) (3/4) parameter symbol conditions min. typ. max. unit input voltage, high v ih1 normal input buffer 20-, 24-pin products: p00 to p03 note 2 , p10 to p14, p40 to p42 30-pin products: p00, p01, p10 to p17, p30, p31, p40, p50, p51, p120, p147 0.8v dd v dd v v ih2 ttl input buffer 20-, 24-pin products: p10, p11 30-pin products: p01, p10, p11, p13 to p17 4.0 v v dd 5.5 v 2.2 v dd v 3.3 v v dd < 4.0 v 2.0 v dd v 1.8 v v dd < 3.3 v 1.5 v dd v v ih3 p20 to p23 0.7v dd v dd v v ih4 p60, p61 0.7v dd 6.0 v v ih5 p121, p122, p125 note 1 , p137, exclk, reset 0.8v dd v dd v input voltage, low v il1 normal input buffer 20-, 24-pin products: p00 to p03 note 2 , p10 to p14, p40 to p42 30-pin products: p00, p01, p10 to p17, p30, p31, p40, p50, p51, p120, p147 0 0.2v dd v v il2 ttl input buffer 20-, 24-pin products: p10, p11 30-pin products: p01, p10, p11, p13 to p17 4.0 v v dd 5.5 v 0 0.8 v 3.3 v v dd < 4.0 v 0 0.5 v 1.8 v v dd < 3.3 v 0 0.32 v v il3 p20 to p23 0 0.3v dd v v il4 p60, p61 0 0.3v dd v v il5 p121, p122, p125 note 1 , p137, exclk, reset 0 0.2v dd v output voltage, high v oh1 20-, 24-pin products: p00 to p03 note 2 , p10 to p14, p40 to p42 30-pin products: p00, p01, p10 to p17, p30, p31, p40, p50, p51, p120, p147 4.0 v v dd 5.5 v, i oh1 = ? 10.0 ma v dd ? 1.5 v 4.0 v v dd 5.5 v, i oh1 = ? 3.0 ma v dd ? 0.7 v 2.7 v v dd 5.5 v, i oh1 = ? 2.0 ma v dd ? 0.6 v 1.8 v v dd 5.5 v, i oh1 = ? 1.5 ma v dd ? 0.5 v v oh2 p20 to p23 i oh2 = ?100 a v dd ? 0.5 v notes 1. 20, 24-pin products only. 2. 24-pin products only. caution the maximum value of v ih of pins p10 to p12 and p41 for 20-pi n products, p01, p10 to p12, and p41 for 24-pin products, and p00, p10 to p15, p17, and p50 for 30-pin products is v dd even in n-ch open- drain mode. high level is not output in the n-ch open-drain mode. remark unless specified otherwise, the characteristics of alte rnate-function pins are the same as those of the port pins. rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 22 of 106 (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) (4/4) parameter symbol conditions min. typ. max. unit output voltage, low v ol1 20-, 24-pin products: p00 to p03 note , p10 to p14, p40 to p42 30-pin products: p00, p01, p10 to p17, p30, p31, p40, p50, p51, p120, p147 4.0 v v dd 5.5 v, i ol1 = 20.0 ma 1.3 v 4.0 v v dd 5.5 v, i ol1 = 8.5 ma 0.7 v 2.7 v v dd 5.5 v, i ol1 = 3.0 ma 0.6 v 2.7 v v dd 5.5 v, i ol1 = 1.5 ma 0.4 v 1.8 v v dd 5.5 v, i ol1 = 0.6 ma 0.4 v v ol2 p20 to p23 i ol2 = 400 a 0.4 v v ol3 p60, p61 4.0 v v dd 5.5 v, i ol1 = 15.0 ma 2.0 v 4.0 v v dd 5.5 v, i ol1 = 5.0 ma 0.4 v 2.7 v v dd 5.5 v, i ol1 = 3.0 ma 0.4 v 1.8 v v dd 5.5 v, i ol1 = 2.0 ma 0.4 v input leakage current, high i lih1 other than p121, p122 v i = v dd 1 a i lih2 p121, p122 (x1, x2/exclk) v i = v dd input port or external clock input 1 a when resonator connected 10 a input leakage current, low i lil1 other than p121, p122 v i = v ss ?1 a i lil2 p121, p122 (x1, x2/exclk) v i = v ss input port or external clock input ?1 a when resonator connected ?10 a on-chip pull-up resistance r u 20-, 24-pin products: p00 to p03 note , p10 to p14, p40 to p42, p125, reset 30-pin products: p00, p01, p10 to p17, p30, p31, p40, p50, p51, p120, p147 v i = v ss , input port 10 20 100 k note 24-pin products only. remark unless specified otherwise, the characteristics of alte rnate-function pins are the same as those of the port pins. rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 23 of 106 2.3.2 supply current characteristics (1) 20-, 24-pin products (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit supply current note 1 i dd1 operating mode hs(high-speed main) mode note 4 f ih = 24 mhz note 3 basic operation v dd = 5.0 v 1.5 ma v dd = 3.0 v 1.5 normal operation v dd = 5.0 v 3.3 5.0 ma v dd = 3.0 v 3.3 5.0 f ih = 16 mhz note 3 v dd = 5.0 v 2.5 3.7 ma v dd = 3.0 v 2.5 3.7 ls(low-speed main) mode note 4 f ih = 8 mhz note 3 v dd = 3.0 v 1.2 1.8 ma v dd = 2.0 v 1.2 1.8 hs(high-speed main) mode note4 f mx = 20 mhz note 2 , v dd = 5.0 v square wave input 2.8 4.4 ma resonator connection 3.0 4.6 f mx = 20 mhz note 2 , v dd = 3.0 v square wave input 2.8 4.4 ma resonator connection 3.0 4.6 f mx = 10 mhz note 2 , v dd = 5.0 v square wave input 1.8 2.6 ma resonator connection 1.8 2.6 f mx = 10 mhz note 2 , v dd = 3.0 v square wave input 1.8 2.6 ma resonator connection 1.8 2.6 ls(low-speed main) mode note 4 f mx = 8 mhz note 2 , v dd = 3.0 v square wave input 1.1 1.7 ma resonator connection 1.1 1.7 f mx = 8 mhz note 2 , v dd = 2.0 v square wave input 1.1 1.7 ma resonator connection 1.1 1.7 notes 1. total current flowing into v dd , including the input leakage current flow ing when the level of the input pin is fixed to v dd or v ss . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d converter, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. when high-speed on-chip oscillator clock is stopped. 3. when high-speed system clock is stopped 4. relationship between operation voltage width, oper ation frequency of cpu and operation mode is as follows. hs(high speed main) mode: v dd = 2.7 v to 5.5 v @1 mhz to 24 mhz v dd = 2.4 v to 5.5 v @1 mhz to 16 mhz ls(low speed main) mode: v dd = 1.8 v to 5.5 v @1 mhz to 8 mhz remarks 1. f mx : high-speed system clock frequency (x1 clock oscilla tion frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. temperature condition of the typ. value is t a = 25 c. rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 24 of 106 (1) 20-, 24-pin products (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit supply current note 1 i dd2 note 2 halt mode hs (high-speed main) mode note 6 f ih = 24 mhz note 4 v dd = 5.0 v 440 1210 a v dd = 3.0 v 440 1210 f ih = 16 mhz note 4 v dd = 5.0 v 400 950 a v dd = 3.0 v 400 950 ls (low-speed main) mode note 6 f ih = 8 mhz note 4 v dd = 3.0 v 270 542 a v dd = 2.0 v 270 542 hs (high-speed main) mode note 6 f mx = 20 mhz note 3 , v dd = 5.0 v square wave input 280 1000 a resonator connection 450 1170 f mx = 20 mhz note 3 , v dd = 3.0 v square wave input 280 1000 a resonator connection 450 1170 f mx = 10 mhz note 3 , v dd = 5.0 v square wave input 190 590 a resonator connection 260 660 f mx = 10 mhz note 3 , v dd = 3.0 v square wave input 190 590 a resonator connection 260 660 ls (low-speed main) mode note 6 f mx = 8 mhz note 3 , v dd = 3.0 v square wave input 110 360 a resonator connection 150 416 f mx = 8 mhz note 3 , v dd = 2.0 v square wave input 110 360 a resonator connection 150 416 i dd3 note 5 stop mode t a = ?40 c 0.19 0.50 a t a = +25 c 0.24 0.50 t a = +50 c 0.32 0.80 t a = +70 c 0.48 1.20 t a = +85 c 0.74 2.20 notes 1. total current flowing into v dd , including the input leakage current flow ing when the level of the input pin is fixed to v dd or v ss . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d converter, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. during halt instruction execution by flash memory. 3. when high-speed on-chip oscillator clock is stopped. 4. when high-speed system clock is stopped. 5. not including the current flowing into the 12-bit interval timer and watchdog timer. 6. relationship between operation voltage width, operation frequency of cpu and operation mode is as follows. hs(high speed main) mode: v dd = 2.7 v to 5.5 v @1 mhz to 24 mhz v dd = 2.4 v to 5.5 v @1 mhz to 16 mhz ls(low speed main) mode: v dd = 1.8 v to 5.5 v @1 mhz to 8 mhz remarks 1. f mx : high-speed system clock frequency (x1 clock oscilla tion frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. except temperature conditi on of the typ. value is t a = 25 c, other than stop mode rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 25 of 106 (2) 30-pin products (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit supply current note 1 i dd1 operating mode hs (high-speed main) mode note 4 f ih = 24 mhz note 3 basic operation v dd = 5.0 v 1.5 ma v dd = 3.0 v 1.5 normal operation v dd = 5.0 v 3.7 5.5 ma v dd = 3.0 v 3.7 5.5 f ih = 16 mhz note 3 v dd = 5.0 v 2.7 4.0 ma v dd = 3.0 v 2.7 4.0 ls (low-speed main) mode note 4 f ih = 8 mhz note 3 v dd = 3.0 v 1.2 1.8 ma v dd = 2.0 v 1.2 1.8 hs (high-speed main) mode note 4 f mx = 20 mhz note 2 , v dd = 5.0 v square wave input 3.0 4.6 ma resonator connection 3.2 4.8 f mx = 20 mhz note 2 , v dd = 3.0 v square wave input 3.0 4.6 ma resonator connection 3.2 4.8 f mx = 10 mhz note 2 , v dd = 5.0 v square wave input 1.9 2.7 ma resonator connection 1.9 2.7 f mx = 10 mhz note 2 , v dd = 3.0 v square wave input 1.9 2.7 ma resonator connection 1.9 2.7 ls (low-speed main) mode note 4 f mx = 8 mhz note 2 , v dd = 3.0 v square wave input 1.1 1.7 ma resonator connection 1.1 1.7 f mx = 8 mhz note 2 , v dd = 2.0 v square wave input 1.1 1.7 ma resonator connection 1.1 1.7 notes 1. total current flowing into v dd , including the input leakage current flowin g when the level of the input pin is fixed to v dd or v ss . the values below the max. column include the peripheral operation current. however, not including the cu rrent flowing into the a/d converter, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. when high-speed on-chip oscillator clock is stopped. 3. when high-speed system clock is stopped 4. relationship between operation voltage width, operation frequency of cpu and operation mode is as follows. hs(high speed main) mode: v dd = 2.7 v to 5.5 v @1 mhz to 24 mhz v dd = 2.4 v to 5.5 v @1 mhz to 16 mhz ls(low speed main) mode: v dd = 1.8 v to 5.5 v @1 mhz to 8 mhz remarks 1. f mx : high-speed system clock frequency (x1 clock oscilla tion frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. temperature condition of the typ. value is t a = 25 c. rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 26 of 106 (2) 30-pin products (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit supply current note 1 i dd2 note 2 halt mode hs (high-speed main) mode note 6 f ih = 24 mhz note 4 v dd = 5.0 v 440 1280 a v dd = 3.0 v 440 1280 f ih = 16 mhz note 4 v dd = 5.0 v 400 1000 a v dd = 3.0 v 400 1000 ls (low-speed main) mode note 6 f ih = 8 mhz note 4 v dd = 3.0 v 260 530 a v dd = 2.0 v 260 530 hs (high-speed main) mode note 6 f mx = 20 mhz note 3 , v dd = 5.0 v square wave input 280 1000 a resonator connection 450 1170 f mx = 20 mhz note 3 , v dd = 3.0 v square wave input 280 1000 a resonator connection 450 1170 f mx = 10 mhz note 3 , v dd = 5.0 v square wave input 190 600 a resonator connection 260 670 f mx = 10 mhz note 3 , v dd = 3.0 v square wave input 190 600 a resonator connection 260 670 ls (low-speed main) mode note 6 f mx = 8 mhz note 3 , v dd = 3.0 v square wave input 95 330 a resonator connection 145 380 f mx = 8 mhz note 3 v dd = 2.0 v square wave input 95 330 a resonator connection 145 380 i dd3 note 5 stop mode t a = ?40 c 0.18 0.50 a t a = +25 c 0.23 0.50 t a = +50 c 0.30 1.10 t a = +70 c 0.46 1.90 t a = +85 c 0.75 3.30 notes 1. total current flowing into v dd , including the input leakage current flowin g when the level of the input pin is fixed to v dd or v ss . the values below the max. column include the peripheral operation current. however, not including the cu rrent flowing into the a/d converter, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. during halt instruction execution by flash memory. 3. when high-speed on-chip oscillator clock is stopped. 4. when high-speed system clock is stopped. 5. not including the current flowing into the 12-bit interval timer and watchdog timer. 6. relationship between operation voltage width, operation frequency of cpu and operation mode is as follows. hs (high speed main) mode: v dd = 2.7 v to 5.5 v @1 mhz to 24 mhz v dd = 2.4 v to 5.5 v @1 mhz to 16 mhz ls (low speed main) mode: v dd = 1.8 v to 5.5 v @1 mhz to 8 mhz remarks 1. f mx : high-speed system clock frequency (x1 clock oscilla tion frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. except stop mode, temperature c ondition of the typ. value is t a = 25 c. rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 27 of 106 (3) peripheral functions (common to all products) (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit low-speed onchip oscillator operating current i fil note 1 0.20 a 12-bit interval timer operating current i tmka notes 1, 2, 3 0.02 a watchdog timer operating current i wdt notes 1, 2, 4 f il = 15 khz 0.22 a a/d converter operating current i adc notes 1, 5 when conversion at maximum speed normal mode, av refp = v dd = 5.0 v 1.30 1.70 ma low voltage mode, av refp = v dd = 3.0 v 0.50 0.70 ma a/d converter reference voltage operating current i adref note 1 75.0 a temperature sensor operating current i tmps note 1 75.0 a lvd operating current i lvd notes 1, 6 0.08 a self- programming operating current i fsp notes 1, 8 2.00 12.20 ma bgo operating current i bgo notes 1, 7 2.00 12.20 ma snooze operating current i snoz note 1 adc operation the mode is performed note 9 0.50 0.60 ma the a/d conversion operations are performed, low voltage mode, av refp = v dd = 3.0 v 1.20 1.44 ma csi/uart operation 0.70 0.84 ma notes 1. current flowing to the v dd. 2. when high speed on-chip oscillator and high-speed system clock are stopped. 3. current flowing only to the 12-bit interval timer (e xcluding the operating current of the low-speed on-chip oscillator). the current value of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 , and i fil and i tmka when the 12-bit interval timer operates. 4. current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). the current value of the rl78 mi crocontrollers is the sum of i dd1 , i dd2 or i dd3 and i wdt when the watchdog timer operates. 5. current flowing only to the a/d converter. the current value of the rl78 microcontrollers is the sum of i dd1 or i dd2 and i adc when the a/d converter operates in an operation mode or the halt mode. 6. current flowing only to the lvd circuit. the current value of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i lvd when the lvd circuit operates. 7. current flowing only during data flash rewrite. 8. current flowing only during self programming. 9. for shift time to the snooze mode, see 17.3.3 snooze mode in the rl 78/g12 user?s manual hardware . remarks 1. f il : low-speed on-chip oscillator clock frequency 2. temperature condition of the typ. value is t a = 25 c rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 28 of 106 2.4 ac characteristics (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit instruction cycle (minimum instruction execution time) t cy main system clock (f main ) operation hs (high- speed main) mode 2.7 v v dd 5.5 v 0.04167 1 s 2.4 v v dd < 2.7 v 0.0625 1 s ls (low- speed main) mode 1.8 v v dd 5.5 v 0.125 1 s during self programming hs (high- speed main) mode 2.7 v v dd 5.5 v 0.04167 1 s 2.4 v v dd < 2.7 v 0.0625 1 s ls (low- speed main) mode 1.8 v v dd 5.5 v 0.125 1 s external main system clock frequency f ex 2.7 v v dd 5.5 v 1.0 20.0 mhz 2.4 v v dd < 2.7 v 1.0 16.0 mhz 1.8 v v dd < 2.4 v 1.0 8.0 mhz external main system clock input high-level width, low- level width t exh , t exl 2.7 v v dd 5.5 v 24 ns 2.4 v v dd < 2.7 v 30 ns 1.8 v v dd < 2.4 v 60 ns ti00 to ti07 input high-level width, low-level width t tih , t til 1/f mck + 10 ns to00 to to07 output frequency f to 4.0 v v dd 5.5 v 12 mhz 2.7 v v dd < 4.0 v 8 mhz 1.8 v v dd < 2.7 v 4 mhz pclbuz0, or pclbuz1 output frequency f pcl 4.0 v v dd 5.5 v 16 mhz 2.7 v v dd < 4.0 v 8 mhz 1.8 v v dd < 2.7 v 4 mhz intp0 to intp5 input high- level width, low-level width t inth , t intl 1 s kr0 to kr9 input available width t kr 250 ns reset low-level width t rsl 10 s remark f mck : timer array unit operation clock frequency (operation clock to be set by the timer clock select register 0 (tps0) and the cks0n bit of timer mode register 0n (tmr0n). n: channel number (n = 0 to 7)) rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 29 of 106 minimum instruction execution time during main system clock operation t cy vs v dd (hs (high-speed main) mode) when the high-speed on-chip oscillator clock is selected during self programming when high-speed system clock is selected supply voltage v dd [v] 1.0 0.1 0 10 1.02 .03 .0 4.05 .06 .0 5.5 2.7 0.01 2.4 0.04167 0.0625 cycle time t cy [s] t cy vs v dd (ls (low-speed main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 0.01 1.8 0.125 cycle time t cy [s] supply voltage v dd [v] when the high-speed on-chip oscillator clock is selected during self programming when high-speed system clock is selected rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 30 of 106 ac timing test point v ih /v oh v il /v ol test points v ih /v oh v il /v ol external main system clock timing exclk 1/f ex t exl t exh ti/to timing ti00 to ti07 t til t tih to00 to to07 1/f to interrupt request input timing intp0 to intp5 t intl t inth key interrupt input timing kr0 to kr9 t kr reset input timing reset t rsl rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 31 of 106 2.5 peripheral functions characteristics ac timing test point v ih /v oh v il /v ol test points v ih /v oh v il /v ol 2.5.1 serial array unit (1) during communication at same potential (uart mode) (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. transfer rate note 1 f mck /6 f mck /6 bps theoretical value of the maximum transfer rate f clk = f mck note2 4.0 1.3 mbps notes 1. transfer rate in the snooze mode is 4800 bps only. 2. the maximum operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main ) mode: 24 mhz (2.7 v v dd 5.5 v) 16 mhz (2.4 v v dd 5.5 v) ls (low-speed main) mode: 8 mhz (1.8 v v dd 5.5 v) caution select the normal input buffer for the rxdq pin and the normal output mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). uart mode connection diagram (during communication at same potential) rl78 microcontroller txdq rxdq rx tx user's device uart mode bit width (during communication at same potential) (reference) txdq rxdq baud rate error tolerance high-/low-bit width 1/transfer rate remarks 1. q: uart number (q = 0 to 2), g: pim, pom number (g = 0, 1) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the serial clock se lect register m (spsm) and the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10, 11)) rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 32 of 106 (2) during communication at same potential (csi mode ) (master mode, sck00... internal clock output, corresponding csi00 only) (t a = ? 40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. sck00 cycle time t kcy1 t kcy1 2/f clk 83.3 250 ns sck00 high-/low- level width t kh1 , t kl1 4.0 v v dd 5.5 v t kcy1 /2? 7 t kcy1 /2? 50 ns 2.7 v v dd 5.5 v t kcy1 /2? 10 t kcy1 /2? 50 ns si00 setup time (to sck00 ) note 1 t sik1 4.0 v v dd 5.5 v 23 110 ns 2.7 v v dd 5.5 v 33 110 ns si00 hold time (from sck00 ) note2 t ksi1 10 10 ns delay time from sck00 to so00 output note 3 t kso1 c = 20 pf note 4 10 10 ns notes 1. when dap00 = 0 and ckp00 = 0, or dap00 = 1 and ckp00 = 1. the si00 setup time becomes ?to sck00 ? when dap00 = 0 and ckp00 = 1, or dap00 = 1 and ckp00 = 0. 2. when dap00 = 0 and ckp00 = 0, or dap00 = 1 and ckp00 = 1. the si00 hold time becomes ?from sck00 ? when dap00 = 0 and ckp00 = 1, or dap00 = 1 and ckp00 = 0. 3. when dap00 = 0 and ckp00 = 0, or dap00 = 1 and c kp00 = 1. the delay time to so00 output becomes ?from sck00 ? when dap00 = 0 and ckp00 = 1, or dap00 = 1 and ckp00 = 0. 4. c is the load capacitance of the sck00 and so00 output lines. caution select the normal input buffer for the si00 pi n and the normal output mode for the so00 and sck00 pins by using port input mode register 1 (pim1) and port output mode register 1 (pom1). remarks 1. this specification is valid only when csi00?s peripheral i/o r edirect function is not used. 2. f mck : serial array unit operation clock frequency (operation clock to be set by the serial clock select register 0 (sps0 ) and the cks00 bit of serial mode register 00 (smr00).) rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 33 of 106 (3) during communication at same pot ential (csi mode) (master mode , sckp... internal clock output) (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. sckp cycle time t kcy1 t kcy1 4/f clk 2.7 v v dd 5.5 v 167 500 ns 2.4 v v dd 5.5 v 250 500 ns 1.8 v v dd 5.5 v ? 500 ns sckp high-/low-level width t kh1 , t kl1 4.0 v v dd 5.5 v t kcy1 /2? 12 t kcy1 /2? 50 ns 2.7 v v dd 5.5 v t kcy1 /2? 18 t kcy1 /2? 50 ns 2.4 v v dd 5.5 v t kcy1 /2? 38 t kcy1 /2? 50 ns 1.8 v v dd 5.5 v ? t kcy1 /2? 50 ns sip setup time (to sckp ) note 1 t sik1 4.0 v v dd 5.5 v 44 110 ns 2.7 v v dd 5.5 v 44 110 ns 2.4 v v dd 5.5 v 75 110 ns 1.8 v v dd 5.5 v ? 110 ns sip hold time (from sckp ) note 2 t ksi1 19 19 ns delay time from sckp to sop output note 3 t kso1 c = 30 pf note4 25 25 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for the sip pin and the normal output mode for the sop and sckp pins by using port input mode register 1 (pim1) and port output mode registers 0, 1, 4 (pom0, pom1, pom4). remarks 1. p: csi number (p = 00, 01, 11, 20), m: unit number (m = 0, 1), n: channel number (n = 0, 1, 3: ?1, 3? is only for the r5f102 products) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the serial clock sele ct register m (spsm) and the cksmn bit of serial mode register mn (smrmn). m: unit number (m = 0, 1), n: channel number (n = 0, 1, 3: ?1, 3? is only for the r5f102 products.)) rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 34 of 106 (4) during communication at same potential (csi mode) (slave mode, sckp... external clock input) (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. sckp cycle time note4 t kcy2 4.0 v v dd 5.5 v 20 mhz < f mck 8/f mck ? ns f mck 20 mhz 6/f mck 6/f mck ns 2.7 v v dd 5.5 v 16 mhz < f mck 8/f mck ? ns f mck 16 mhz 6/f mck 6/f mck ns 2.4 v v dd 5.5 v 6/f mck and 500 6/f mck and 500 ns 1.8 v v dd 5.5 v ? 6/f mck and 750 ns sckp high-/low-level width t kh2 , t kl2 4.0 v v dd 5.5 v t kcy2 /2? 7 t kcy2 /2? 7 ns 2.7 v v dd 5.5 v t kcy2 /2? 8 t kcy2 /2? 8 ns 2.4 v v dd 5.5 v t kcy2 /2? 18 t kcy2 /2? 18 ns 1.8 v v dd 5.5 v ? t kcy2 /2? 18 ns sip setup time (to sckp ) note 1 t sik2 2.7 v v dd 5.5 v 1/f mck + 20 1/f mck + 30 ns 2.4 v v dd 5.5 v 1/f mck + 30 1/f mck + 30 ns 1.8 v v dd 5.5 v ? 1/f mck + 30 ns sip hold time (from sckp ) note 2 t ksi2 1/f mck + 31 1/f mck + 31 ns delay time from sckp to sop output note 3 t kso2 c = 30 pf note4 2.7 v v dd 5.5 v 2/f mck + 44 2/f mck + 110 ns 2.4 v v dd 5.5 v 2/f mck + 75 2/f mck + 110 ns 1.8 v v dd 5.5 v ? 2/f mck + 110 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitanc e of the sop output lines. 5. transfer rate in the snooze mode: max. 1 mbps caution select the normal input buffer for the sip and sckp pins and the normal output mode for the sop pin by using port input mode register 1 (pim1) and port output mode registers 0, 1, 4 (pom0, pom1, pom4). rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 35 of 106 csi mode connection diagram (duri ng communication at same potential) rl78 microcontroller sckp sop sck si user's device sip so csi mode serial transfer timing (dur ing communication at same potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) si p sop t kcy1, 2 t kl1, 2 t kh1, 2 t si k1 , 2 t ksi1, 2 t kso1, 2 sckp input data output data csi mode serial transfer timing (dur ing communication at same potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) si p sop t kcy1, 2 t kh1, 2 t kl1, 2 t si k1 , 2 t ksi1, 2 t kso1, 2 sckp input data out put dat a ( remarks are listed on the next page.) rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 36 of 106 remarks 1. p: csi number (p = 00, 01, 11, 20), m: unit number (m = 0, 1), n: channel number (n = 0, 1, 3: ?1, 3? is only for the r5f102 products.) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the serial clock select register m (spsm) and the cksmn bit of serial mode register mn (smrmn). m: unit number (m = 0, 1), n: channel number (n = 0, 1, 3: ?1, 3? is only for the r5f102 products.)) (5) during communication at same potential (simplified i 2 c mode) (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. sclr clock frequency f scl 1.8 v v dd 5.5 v, c b = 100 pf, r b = 3 k 400 note 1 khz 1.8 v v dd < 2.7 v, c b = 100 pf, r b = 5 k 300 note 1 khz hold time when sclr = ?l? t low 1.8 v v dd 5.5 v, c b = 100 pf, r b = 3 k 1150 ns 1.8 v v dd < 2.7 v, c b = 100 pf, r b = 5 k 1550 ns hold time when sclr = ?h? t high 1.8 v v dd 5.5 v, c b = 100 pf, r b = 3 k 1150 ns 1.8 v v dd < 2.7 v, c b = 100 pf, r b = 5 k 1550 ns data setup time (reception) t su:dat 1.8 v v dd 5.5 v, c b = 100 pf, r b = 3 k 1/f mck + 145 note 2 ns 1.8 v v dd < 2.7 v, c b = 100 pf, r b = 5 k 1/f mck + 230 note 2 ns data hold time (transmission) t hd:dat 1.8 v v dd 5.5 v, c b = 100 pf, r b = 3 k 0 355 ns 1.8 v v dd < 2.7 v, c b = 100 pf, r b = 5 k 0 405 ns notes 1. the value must also be equal to or less than f mck /4. 2. set t su:dat so that it will not exceed the hold ti me when sclr = "l" or sclr = "h". caution select the n-ch open drain output (v dd tolerance) mode for sdar by using port output mode register h (pomh). ( remarks are listed on the next page.) rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 37 of 106 simplified i 2 c mode connection diagram (during communication at same potential) rl78 microcontroller sdar sclr sda scl user's device v dd r b simplified i 2 c mode serial transfer timing (during communication at same potential) sdar t low t high t hd:dat sclr t su:dat 1/f scl remarks 1. r b [ ]:communication line (sdar) pull-up resistance c b [f]: communication line (sclr, sdar) load capacitance 2. r: iic number (r = 00, 01, 11, 20), h: = pom number (h = 0, 1, 4, 5) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the serial clock se lect register m (spsm) and the cksmn bit of serial mode register mn (smrmn). m: unit number (m = 0, 1), n: channel number (0, 1, 3)) 4. simplified i 2 c mode is supported only by the r5f102 products. rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 38 of 106 (6) communication at different potential (1.8 v, 2.5 v, 3 v) (uart mode) (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. transfer rate note4 reception 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v f mck /6 note1 f mck /6 note1 bps theoretical value of the maximum transfer rate f mck = f clk note3 4.0 1.3 mbps 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v f mck /6 note1 f mck /6 note1 bps theoretical value of the maximum transfer rate f mck = f clk note3 4.0 1.3 mbps 1.8 v v dd < 3.3 v, 1.6 v v b 2.0 v f mck /6 notes1, 2 f mck /6 notes1, 2 bps theoretical value of the maximum transfer rate f mck = f clk note3 4.0 1.3 mbps transmission 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v note4 note4 bps theoretical value of the maximum transfer rate c b = 50 pf, r b = 1.4 k , v b = 2.7 v 2.8 note5 2.8 note5 mbps 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, note6 note6 bps theoretical value of the maximum transfer rate c b = 50 pf, r b = 2.7 k , v b = 2.3 v 1.2 note7 1.2 note7 mbps 1.8 v v dd < 3.3 v, 1.6 v v b 2.0 v notes 2, 8 notes 2, 8 bps theoretical value of the maximum transfer rate c b = 50 pf, r b = 5.5 k , v b = 1.6 v 0.43 note9 0.43 note9 mbps notes 1. transfer rate in the snooze mode is 4800 bps only. 2. use it with v dd v b . 3. the maximum operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main ) mode: 24 mhz (2.7 v v dd 5.5 v) 16 mhz (2.4 v v dd 5.5 v) ls (low-speed main) mode: 8 mhz (1.8 v v dd 5.5 v) 4. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 4.0 v v dd 5.5 v and 2.7 v v b 4.0 v maximum transfer rate = 1 [bps] { ?c b r b ln (1 ? 2.2 v b )} 3 1 transfer rate 2 ? { ?c b r b ln (1 ? 2.2 v b )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical value of the relative difference betwe en the transmission and reception sides. rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 39 of 106 5. this value as an example is calculated when the condi tions described in the ?conditions? column are met. refer to note 4 above to calculate the maximum transfer rate under conditions of the customer. 6. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.7 v v dd < 4.0 v and 2.3 v v b 2.7 v maximum transfer rate = 1 [bps] { ?c b r b ln (1 ? 2.0 v b )} 3 1 transfer rate 2 ? { ?c b r b ln (1 ? 2.0 v b )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical value of the relative difference betwe en the transmission and reception sides. 7. this value as an example is calculated when the condi tions described in the ?conditions? column are met. refer to note 6 above to calculate the maximum transfer rate under conditions of the customer. 8. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 1.8 v v dd < 3.3 v, 1.6 v v b 2.0 v maximum transfer rate = 1 [bps] { ?c b r b ln (1 ? 1.5 v b )} 3 1 transfer rate 2 ? { ?c b r b ln (1 ? 1.5 v b )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical value of the relative difference betwe en the transmission and reception sides. 9. this value as an example is calculated when the condi tions described in the ?conditions? column are met. refer to note 8 above to calculate the maximum transfer rate under conditions of the customer. caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance) mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 40 of 106 uart mode connection diagram (during communication at different potential) rl78 microcontroller txdq rxdq rx tx user's device v b r b uart mode bit width (during communication at different potential) (reference) txdq rxdq baud rate error tolerance high-/low-bit width 1/transfer rate baud rate error tolerance high-bit width low-bit width 1/transfer rate remarks 1. r b [ ]: communication line (txdq) pull-up resistance, c b [f]: communication line (txdq) load capacitance, v b [v]: communication line voltage 2. q: uart number (q = 0 to 2), g: pim and pom number (g = 0, 1) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the serial clock sele ct register m (spsm) and the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10, 11)) 4. uart0 of the 20- and 24-pin products supports communication at different potential only when the peripheral i/o redirection function is not used. rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 41 of 106 (7) communication at different potential (2.5 v, 3 v) (c si mode) (master mode, sck 00... internal clock output, corresponding csi00 only) (t a = ? 40 to +85 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. sck00 cycle time t kcy1 t kcy1 2/f clk 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 200 1150 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 300 1150 ns sck00 high-level width t kh1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k t kcy1 /2 ? 50 t kcy1 /2? 50 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k t kcy1 /2 ? 120 t kcy1 /2 ? 120 ns sck00 low-level width t kl1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k t kcy1 /2 ? 7 t kcy1 /2 ? 50 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k t kcy1 /2 ? 10 t kcy1 /2 ? 50 ns si00 setup time (to sck00 ) note 1 t sik1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 58 479 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 121 479 ns si00 hold time (from sck00 ) note 1 t ksi1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 10 10 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 10 10 ns delay time from sck00 to so00 output note 1 t kso1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 60 60 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 130 130 ns si00 setup time (to sck00 ) note 2 t sik1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 23 110 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 33 110 ns si00 hold time (from sck00 ) note 2 t ksi1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 10 10 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 10 10 ns delay time from sck00 to so00 output note 2 t kso1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 10 10 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 10 10 ns (notes , caution , and remarks are listed on the next page.) rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 42 of 106 notes 1. when dap00 = 0 and ckp00 = 0, or dap00 = 1 and ckp00 = 1 2. when dap00 = 0 and ckp00 = 1, or dap00 = 1 and ckp00 = 0. caution select the ttl input buffer for the si00 pin and the n-ch open drain output (v dd tolerance) mode for the so00 pin and sck00 pin by using port input mode register 1 (pim1) and port output mode register 1 (pom1). for v ih and v il , see the dc characteristics with ttl input buffer selected. remarks 1. r b [ ]:communication line (sck00, so00) pull-up resistance, c b [f]: communication line (sck00, so00) load capacitance, v b [v]: communication line voltage 2. f mck : serial array unit operation clock frequency (operation clock to be set by the serial clock select register 0 (sps0 ) and the cks00 bit of serial mode register 00 (smr00).) rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 43 of 106 (8) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output) (1/3) (t a = ? 40 to +85 c, 1.8 v v dd v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. sckp cycle time t kcy1 t kcy1 4/f clk 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 300 1150 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 500 1150 ns 1.8 v v dd < 3.3 v, 1.6 v v b 2.0 v note , c b = 30 pf, r b = 5.5 k 1150 1150 ns sckp high-level width t kh1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k t kcy1 /2 ? 75 t kcy1 /2? 75 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 ? 170 t kcy1 /2? 170 ns 1.8 v v dd < 3.3 v, 1.6 v v b 2.0 v note , c b = 30 pf, r b = 5.5 k t kcy1 /2 ? 458 t kcy1 /2? 458 ns sckp low-level width t kl1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k t kcy1 /2 ? 12 t kcy1 /2? 50 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 ? 18 t kcy1 /2? 50 ns 1.8 v v dd < 3.3 v, 1.6 v v b 2.0 v note , c b = 30 pf, r b = 5.5 k t kcy1 /2 ? 50 t kcy1 /2? 50 ns note use it with v dd v b . cautions 1. select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register 1 (pim1) and port output mode register 1 (pom1). for v ih and v il , see the dc characteristics with ttl input buffer selected. 2. csi01 and csi11 cannot communicate at different potential. remarks 1. r b [ ]: communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage 2. p: csi number (p = 00, 20) rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 44 of 106 (8) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output) (2/3) (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. sip setup time (to sckp ) note 1 t sik1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 81 479 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 177 479 ns 1.8 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 30 pf, r b = 5.5 k 479 479 ns sip hold time (from sckp ) note 1 t ksi1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 19 19 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 19 19 ns 1.8 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 30 pf, r b = 5.5 k 19 19 ns delay time from sckp to sop output note 1 t kso1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 100 100 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 195 195 ns 1.8 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 30 pf, r b = 5.5 k 483 483 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. 2. use it with v dd v b . ( cautions and remarks are listed on the next page.) rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 45 of 106 (8) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output) (3/3) (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. sip setup time (to sckp ) note 1 t sik1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 44 110 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 44 110 ns 1.8 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 30 pf, r b = 5.5 k 110 110 ns sip hold time (from sckp ) note 1 t ksi1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 19 19 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 19 19 ns 1.8 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 30 pf, r b = 5.5 k 19 19 ns delay time from sckp to sop output note 1 t kso1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 25 25 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 25 25 ns 1.8 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 30 pf, r b = 5.5 k 25 25 ns notes 1. when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. use it with v dd v b . cautions 1. select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register 1 (pim1) and port output mode register 1 (pom1). for v ih and v il , see the dc characteristics with ttl input buffer selected. 2. csi01 and csi11 cannot communicate at different potential. remarks 1. r b [ ]: communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage 2. p: csi number (p = 00, 20), m: unit numbe r (m = 0, 1), n: channel number (n = 0) csi mode connection diagram (during communication at different potential) v b r b sckp sop sck si user's device sip so v b r b rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 46 of 106 csi mode serial transfer timing (master mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1) input data output data sip sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sckp csi mode serial transfer timing (master mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sip sop sckp input data output data rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 47 of 106 (9) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (slave mode, sckp... external clock input) (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. sckp cycle time note 1 t kcy2 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v 20 mhz < f mck 24 mhz 12/f mck ? ns 8 mhz < f mck 20 mhz 10/f mck ? ns 4 mhz < f mck 8 mhz 8/f mck 16/f mck ns f mck 4 mhz 6/f mck 10/f mck ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v 20 mhz < f mck 24 mhz 16/f mck ? ns 16 mhz < f mck 20 mhz 14/f mck ? ns 8 mhz < f mck 16 mhz 12/f mck ? ns 4 mhz < f mck 8 mhz 8/f mck 16/f mck ns f mck 4 mhz 6/f mck 10/f mck ns 1.8 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 20 mhz < f mck 24 mhz 36/f mck ? ns 16 mhz < f mck 20 mhz 32/f mck ? ns 8 mhz < f mck 16 mhz 26/f mck ? ns 4 mhz < f mck 8 mhz 16/f mck 16/f mck ns f mck 4 mhz 10/f mck 10/f mck ns sckp high-/low-level width t kh2 , t kl2 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v t kcy2 /2 ? 12 t kcy2 /2 ? 50 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v t kcy2 /2 ? 18 t kcy2 /2 ? 50 ns 1.8 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 t kcy2 /2 ? 50 t kcy2 /2 ? 50 ns sip setup time (to sckp ) note 3 t sik2 4.0 v v dd 5.5 v, 2.7 v v dd 4.0 v 1/f mck + 20 1/f mck + 30 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v 1/f mck + 20 1/f mck + 30 ns 1.8 v v dd < 3.3 v, 1.6 v v dd 2.0 v note 2 1/f mck + 30 1/f mck + 30 ns sip hold time (from sckp ) note 4 t ksi2 1/f mck + 31 1/f mck + 31 ns delay time from sckp to sop output note 5 t kso2 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 2/f mck + 120 2/f mck + 573 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 2/f mck + 214 2/f mck + 573 ns 1.8 v v dd < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 30 pf, r b = 5.5 k 2/f mck + 573 2/f mck + 573 ns notes 1. transfer rate in the snooze mode: max. 1 mbps 2. use it with v dd v b . 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 5. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. cautions 1. select the ttl input buffer for the sip and sckp pins and the n-ch open drain output (v dd tolerance) mode for the sop pin by using port input mode register 1 (pim1) and port output mode register 1 (pom1). for v ih and v il , see the dc characteristics with ttl input buffer selected. 2. csi01 and csi11 cannot communicate at different potential. rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 48 of 106 csi mode connection diagram (during communication at different potential) rl78 microcontroller sop sck si user's device sip so v b r b sckp rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 49 of 106 csi mode serial transfer timing (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) input data output data sip sop t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2 sckp remark p: csi number (p = 00, 20), m: unit numbe r (m = 0, 1), n: channel number (n = 0) rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 50 of 106 (10) communication at different potential (1.8 v, 2.5 v, 3 v) (simplified i 2 c mode) (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit min. max. min. max. sclr clock frequency f scl 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 400 note1 300 note1 khz 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 400 note1 300 note1 khz 1.8 v v dd < 3.3 v, 1.6 v v b 2.0 v, note2 c b = 100 pf, r b = 5.5 k 300 note1 300 note1 khz hold time when sclr = ?l? t low 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 1150 1550 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 1150 1550 ns 1.8 v v dd < 3.3 v, 1.6 v v b 2.0 v, note2 c b = 100 pf, r b = 5.5 k 1550 1550 ns hold time when sclr = ?h? t high 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 675 610 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 600 610 ns 1.8 v v dd < 3.3 v, 1.6 v v b 2.0 v, note2 c b = 100 pf, r b = 5.5 k 610 610 ns data setup time (reception) t su:dat 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 1/f mck + 190 note3 1/f mck + 190 note3 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 1/f mck + 190 note3 1/f mck + 190 note3 ns 1.8 v v dd < 3.3 v, 1.6 v v b 2.0 v, note2 c b = 100 pf, r b = 5.5 k 1/f mck + 190 note3 1/f mck + 190 note3 ns data hold time (transmission) t hd:dat 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 0 355 0 355 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 0 355 0 355 ns 1.8 v v dd < 3.3 v, 1.6 v v b 2.0 v, note2 c b = 100 pf, r b = 5.5 k 0 405 0 405 ns notes 1. the value must also be equal to or less than f mck /4. 2. use it with v dd v b . 3. set t su:dat so that it will not exceed the hold ti me when sclr = "l" or sclr = "h". cautions 1. select the ttl input buffer and the n-ch open drain output (v dd tolerance) mode for the sdar pin and the n-ch open drain output (v dd tolerance) mode for the sclr pin by using port input mode register 1 (pim1) and port output mode register 1 (pom1). for v ih and v il , see the dc characteristics with ttl input buffer selected. 2. iic01 and iic11 cannot communicate at different potential. ( remarks are listed on the next page.) rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 51 of 106 simplified i 2 c mode connection diagram (during communication at different potential) sdar sclr sda scl user's device v b r b v b r b rl78 microcontroller simplified i 2 c mode serial transfer timing (during communication at different potential) sdar t low t high t hd : dat sclr t su : dat 1/f scl remarks 1. r b [ ]: communication line (sdar, sclr) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance, v b [v]: communication line voltage 2. r: iic number (r = 00, 20) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the serial clock select register m (spsm) and the cksmn bit of serial mode register mn (smrmn). m: unit number (m = 0,1), n: channel number (n = 0)) 4. simplified i 2 c mode is supported only by the r5f102 products. rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 52 of 106 2.5.2 serial interface iica (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode unit standard mode fast mode min. max. min. max. scla0 clock frequency f scl fast mode: f clk 3.5 mhz 0 400 khz normal mode: f clk 1 mhz 0 100 khz setup time of restart condition t su:sta 4.7 0.6 s hold time note 1 t hd:sta 4.0 0.6 s hold time when scla0 = ?l? t low 4.7 1.3 s hold time when scla0 = ?h? t high 4.0 0.6 s data setup time (reception) t su:dat 250 100 ns data hold time (transmission) note 2 t hd:dat 0 3.45 0 0.9 s setup time of stop condition t su:sto 4.0 0.6 s bus-free time t buf 4.7 1.3 s notes 1. the first clock pulse is generated after this per iod when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wa it state is inse rted in the ack (acknowledge) timing. caution only in the 30-pin products, the values in the above table are applied even when bit 2 (pior2) in the peripheral i/o redirection register (pior) is 1. at this time, the pin characteristics (i oh1 , i ol1 , v oh1 , v ol1 ) must satisfy the values in the redirect destination. remark the maximum value of c b (communication line capacitance) and the value of r b (communication line pull-up resistor) at that time in each mode are as follows. normal mode: c b = 400 pf, rb = 2.7 k fast mode: c b = 320 pf, rb = 1.1 k iica serial transfer timing t low t r t high t f t buf t hd:dat t su:dat t hd:sta t su:sta t hd:sta t su:sto scla0 sdaa0 stop condition start condition restart condition stop condition rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 53 of 106 2.6 analog characteristics 2.6.1 a/d converter characteristics classification of a/d converter characteristics input channel reference voltage reference voltage (+) = av refp reference voltage ( ? ) = av refm reference voltage (+) = v dd reference voltage ( ? ) = v ss reference voltage (+) = v bgr reference voltage ( ? ) = av refm ani0 to ani3 refer to 2.6.1 (1) . refer to 2.6.1 (3) . refer to 2.6.1 (4) . ani16 to ani22 refer to 2.6.1 (2) . internal reference voltage temperature sensor output voltage refer to 2.6.1 (1) . ? (1) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target pin: ani2, ani3, internal reference voltage, and temperature sensor output voltage (t a = ? 40 to +85 c, 1.8 v av refp v dd 5.5 v, v ss = 0 v, reference voltage (+) = av refp , reference voltage ( ? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution res 8 10 bit overall error note 1 ainl 10-bit resolution av refp = v dd note 3 1.2 3.5 lsb 1.2 7.0 note 4 lsb conversion time t conv 10-bit resolution target pin: ani2, ani3 3.6 v v dd 5.5 v 2.125 39 s 2.7 v v dd 5.5 v 3.1875 39 s 1.8 v v dd 5.5 v 17 39 s 57 95 s 10-bit resolution target pin: internal reference voltage, and temperature sensor output voltage (hs (high-speed main) mode) 3.6 v v dd 5.5 v 2.375 39 s 2.7 v v dd 5.5 v 3.5625 39 s 2.4 v v dd 5.5 v 17 39 s zero-scale error notes 1, 2 ezs 10-bit resolution av refp = v dd note 3 0.25 %fsr 0.50 note 4 %fsr full-scale error notes 1, 2 efs 10-bit resolution av refp = v dd note 3 0.25 %fsr 0.50 note 4 %fsr integral linearity error note 1 ile 10-bit resolution av refp = v dd note 3 2.5 lsb 5.0 note 4 lsb differential linearity error note 1 dle 10-bit resolution av refp = v dd note 3 1.5 lsb 2.0 note 4 lsb analog input voltage v ain ani2, ani3 0 av refp v internal reference voltage (2.4 v v dd 5.5 v, hs (high-speed main) mode) v bgr note 5 v temperature sensor output voltage (2.4 v v dd 5.5 v, hs (high-speed main) mode) v tmps25 note 5 v (notes are listed on the next page.) rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 54 of 106 notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. when av refp < v dd , the max. values are as follows. overall error: add 1.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add 0.05%fsr to the max. value when av refp = v dd . integral linearity error/ differential linearity error: add 0.5 lsb to the max. value when av refp = v dd . 4. values when the conversi on time is set to 57 s (min.) and 95 s (max.). 5. refer to 2.6.2 temperature sensor/internal reference voltage characteristics . (2) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target pin: ani16 to ani22 (t a = ? 40 to +85 c, 1.8 v av refp v dd 5.5 v, v ss = 0 v, reference voltage (+) = av refp , reference voltage ( ? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 8 10 bit overall error note 1 ainl 10-bit resolution av refp = v dd note 3 1.2 5.0 lsb 1.2 8.5 note 4 lsb conversion time t conv 10-bit resolution target ani pin: ani16 to ani22 3.6 v v dd 5.5 v 2.125 39 s 2.7 v v dd 5.5 v 3.1875 39 s 1.8 v v dd 5.5 v 17 39 s 57 95 s zero-scale error notes 1, 2 ezs 10-bit resolution av refp = v dd note 3 0.35 %fsr 0.60 note 4 %fsr full-scale error notes 1, 2 efs 10-bit resolution av refp = v dd note 3 0.35 %fsr 0.60 note 4 %fsr integral linearity error note 1 ile 10-bit resolution av refp = v dd note 3 3.5 lsb 6.0 note 4 lsb differential linearity error note 1 dle 10-bit resolution av refp = v dd note 3 2.0 lsb 2.5 note 4 lsb analog input voltage v ain ani16 to ani22 0 av refp and v dd v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. when av refp v dd , the max. values are as follows. overall error: add 4.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add 0.20%fsr to the max. value when av refp = v dd . integral linearity error/ differential linearity error: add 2.0 lsb to the max. value when av refp = v dd . 4. when the conversion time is set to 57 s (min.) and 95 s (max.). rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 55 of 106 (3) when reference voltage (+) = v dd (adrefp1 = 0, adrefp0 = 0), reference voltage ( ? ) = v ss (adrefm = 0), target pin: ani0 to ani3, ani16 to ani22, internal reference voltage, and temperature sensor output voltage (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v, reference voltage (+) = v dd , reference voltage ( ? ) = v ss ) parameter symbol conditions min. typ. max. unit resolution r es 8 10 bit overall error note 1 ainl 10-bit resolution 1.2 7.0 lsb 1.2 10.5 note 3 lsb conversion time t conv 10-bit resolution target pin: ani0 to ani3, ani16 to ani22 3.6 v v dd 5.5 v 2.125 39 s 2.7 v v dd 5.5 v 3.1875 39 s 1.8 v v dd 5.5 v 17 39 s 57 95 s conversion time t conv 10-bit resolution target pin: internal reference voltage, and temperature sensor output voltage (hs (high-speed main) mode) 3.6 v v dd 5.5 v 2.375 39 s 2.7 v v dd 5.5 v 3.5625 39 s 2.4 v v dd 5.5 v 17 39 s zero-scale error notes 1, 2 ezs 10-bit resolution 0.60 %fsr 0.85 note 3 %fsr full-scale error notes 1, 2 efs 10-bit resolution 0.60 %fsr 0.85 note 3 %fsr integral linearity error note 1 ile 10-bit resolution 4.0 lsb 6.5 note 3 lsb differential linearity error note 1 dle 10-bit resolution 2.0 lsb 2.5 note 3 lsb analog input voltage v ain ani0 to ani3, ani16 to ani22 0 v dd v internal reference voltage (2.4 v v dd 5.5 v, hs (high-speed main) mode) v bgr note 4 v temperature sensor output voltage (2.4 v v dd 5.5 v, hs (high-speed main) mode) v tmps25 note 4 v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. when the conversion time is set to 57 s (min.) and 95 s (max.). 4. refer to 2.6.2 temperature sensor/internal reference voltage characteristics . rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 56 of 106 (4) when reference voltage (+) = internal reference voltage (adrefp1 = 1, adrefp0 = 0), reference voltage ( ? ) = av refm (adrefm = 1), target pin: ani0 , ani2, ani3, and ani16 to ani22 (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v, reference voltage (+) = v bgr note 3 , reference voltage ( ? ) = av refm note 4 = 0 v, hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit resolution r es 8 bit conversion time t conv 8-bit resolution 17 39 s zero-scale error notes 1, 2 ezs 8-bit resolution 0.60 %fsr integral linearity error note 1 ile 8-bit resolution 2.0 lsb differential linearity error note 1 dle 8-bit resolution 1.0 lsb analog input voltage v ain 0 v bgr note 3 v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. refer to 2.6.2 temperature sensor/internal reference voltage characteristics . 4. when reference voltage ( ? ) = v ss , the max. values are as follows. zero-scale error: add 0.35%fsr to the max. value when reference voltage ( ? ) = av refm . integral linearity error: add 0.5 lsb to the max. value when reference voltage ( ? ) = av refm . differential linearity error: add 0.2 lsb to the max. value when reference voltage ( ? ) = av refm . rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 57 of 106 2.6.2 temperature sensor/internal reference voltage characteristics (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v, hs (high-speed main) mode parameter symbol conditions min. typ. max. unit temperature sensor output voltage v tmps25 setting ads register = 80h, t a = +25 c 1.05 v internal reference voltage v bgr setting ads register = 81h 1.38 1.45 1.50 v temperature coefficient f vtmps temperature sensor output voltage that depends on the temperature ? 3.6 mv/ c operation stabilization wait time t amp 5 s 2.6.3 por circuit characteristics (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage v por power supply rise time 1.47 1.51 1.55 v v pdr power supply fall time 1.46 1.50 1.54 v minimum pulse width note t pw 300 s note minimum time required for a por reset when v dd exceeds below v pdr . this is also the minimum time required for a por reset from when v dd exceeds below 0.7 v to when v dd exceeds v por while stop mode is entered or the main system clock is stopped through setting bi t 0 (hiostop) and bit 7 (msto p) in the clock operation status control register (csc). t pw v por v pdr or 0.7 v supply voltage (v dd ) rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 58 of 106 2.6.4 lvd circuit characteristics lvd detection voltage of reset mode and interrupt mode (t a = ? 40 to +85 c, v pdr v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit detection supply voltage v lvd0 power supply rise time 3.98 4.06 4.14 v power supply fall time 3.90 3.98 4.06 v v lvd1 power supply rise time 3.68 3.75 3.82 v power supply fall time 3.60 3.67 3.74 v v lvd2 power supply rise time 3.07 3.13 3.19 v power supply fall time 3.00 3.06 3.12 v v lvd3 power supply rise time 2.96 3.02 3.08 v power supply fall time 2.90 2.96 3.02 v v lvd4 power supply rise time 2.86 2.92 2.97 v power supply fall time 2.80 2.86 2.91 v v lvd5 power supply rise time 2.76 2.81 2.87 v power supply fall time 2.70 2.75 2.81 v v lvd6 power supply rise time 2.66 2.71 2.76 v power supply fall time 2.60 2.65 2.70 v v lvd7 power supply rise time 2.56 2.61 2.66 v power supply fall time 2.50 2.55 2.60 v v lvd8 power supply rise time 2.45 2.50 2.55 v power supply fall time 2.40 2.45 2.50 v v lvd9 power supply rise time 2.05 2.09 2.13 v power supply fall time 2.00 2.04 2.08 v v lvd10 power supply rise time 1.94 1.98 2.02 v power supply fall time 1.90 1.94 1.98 v v lvd11 power supply rise time 1.84 1.88 1.91 v power supply fall time 1.80 1.84 1.87 v minimum pulse width t lw 300 s detection delay time 300 s rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 59 of 106 lvd detection voltage of interrupt & reset mode (t a = ? 40 to +85 c, v pdr v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit interrupt and reset mode v lvdb0 v poc2 , v poc1 , v poc0 = 0, 0, 1, falling reset voltage 1.80 1.84 1.87 v v lvdb1 lvis1, lvis0 = 1, 0 rising reset release voltage 1.94 1.98 2.02 v falling interrupt voltage 1.90 1.94 1.98 v v lvdb2 lvis1, lvis0 = 0, 1 rising reset release voltage 2.05 2.09 2.13 v falling interrupt voltage 2.00 2.04 2.08 v v lvdb3 lvis1, lvis0 = 0, 0 rising reset release voltage 3.07 3.13 3.19 v falling interrupt voltage 3.00 3.06 3.12 v v lvdc0 v poc2 , v poc1 , v poc0 = 0, 1, 0, falling reset voltage 2.40 2.45 2.50 v v lvdc1 lvis1, lvis0 = 1, 0 rising reset release voltage 2.56 2.61 2.66 v falling interrupt voltage 2.50 2.55 2.60 v v lvdc2 lvis1, lvis0 = 0, 1 rising reset release voltage 2.66 2.71 2.76 v falling interrupt voltage 2.60 2.65 2.70 v v lvdc3 lvis1, lvis0 = 0, 0 rising reset release voltage 3.68 3.75 3.82 v falling interrupt voltage 3.60 3.67 3.74 v v lvdd0 v poc2 , v poc1 , v poc1 = 0, 1, 1, falling reset voltage 2.70 2.75 2.81 v v lvdd1 lvis1, lvis0 = 1, 0 rising reset release voltage 2.86 2.92 2.97 v falling interrupt voltage 2.80 2.86 2.91 v v lvdd2 lvis1, lvis0 = 0, 1 rising reset release voltage 2.96 3.02 3.08 v falling interrupt voltage 2.90 2.96 3.02 v v lvdd3 lvis1, lvis0 = 0, 0 rising reset release voltage 3.98 4.06 4.14 v falling interrupt voltage 3.90 3.98 4.06 v 2.6.5 power supply voltage rising slope characteristics (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit power supply voltage rising slope s vdd 54 v/ms caution make sure to keep the internal reset state by the lvd circuit or an external reset until v dd reaches the operating voltage range shown in 2.4 ac characteristics. rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 60 of 106 2.7 data memory stop mode low supply voltage data retention characteristics (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.46 note 5.5 v note the value depends on the por detection voltage. when the voltage drops, the data is retained before a por reset is affected, but data is not re tained when a por reset is affected. v dd v dddr stop instruction execution standby release signal (interrupt request) stop mode data retention mode operation mode 2.8 flash memory programming characteristics (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit system clock frequency f clk 1 24 mhz code flash memory rewritable times notes 1, 2, 3 c erwr retained for 20 years t a = 85c 1,000 times data flash memory rewritable times notes 1, 2, 3 retained for 1 year t a = 25c 1,000,000 retained for 5 years t a = 85c 100,000 retained for 20 years t a = 85c 10,000 notes 1. 1 erase + 1 write after the erase is regarded as 1 rewr ite. the retaining years are until next rewrite after the rewrite. 2. when using flash memory programmer and renesas electronics self programming library 3. these are the characteristics of t he flash memory and the results obtained from reliability testing by renesas electronics corporation. rl78/g12 2. electrical specifications (a, d: t a = ? 40 to +85 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 61 of 106 2.9 dedicated flash memory programmer communication (uart) (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit transfer rate during serial programming 115,200 1,000,000 bps 2.10 timing of entry to flash memory programming modes (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit time to complete the communication for the initial setting after the external reset is released t suinit por and lvd reset are released before external reset release 100 ms time to release the external reset after the tool0 pin is set to the low level t su por and lvd reset are released before external reset release 10 s time to hold the tool0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) t hd por and lvd reset are released before external reset release 1 ms reset tool0 <1> <2> <3> t suinit t hd + software processing time 1-byte data for setting mode t su <4> <1> the low level is input to the tool0 pin. <2> the external reset is released (por and lvd reset must be released before the external reset is released.). <3> the tool0 pin is set to the high level. <4> setting of the flash memory programming mode by uart reception and complete the baud rate setting. remark t suinit : communication for the initial setting must be completed within 100 ms after the external reset is released during this period. t su : time to release the exte rnal reset after the tool0 pi n is set to the low level t hd : time to hold the tool0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 62 of 106 3. electrical specifications (g: t a = ? 40 to +105 c) this chapter describes the electrical specifications for the products "g: industrial applications (t a = -40 to +105 c)". cautions 1. the rl78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug func tion in products designa ted for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability theref ore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. 2. the pins mounted depend on the product. refer to 2.1 port functi ons to 2.2.1 functions for each product in the rl78/g12 user?s manual hardware. 3. please contact renesas electronics sales office for derating of operation under t a = +85 c to +105 c. derating is the systematic reduction of load for the sake of improved reliability. there are following differences between the products "g: industrial applications (t a = -40 to +105 c)" and the products ?a: consumer applications, and d: industrial applications?. parameter application a: consumer applications, d: industrial applications g: industrial applications operating ambient temperature t a = -40 to +85 c t a = -40 to +105 c operating mode operating voltage range hs (high-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 24 mhz 2.4 v v dd 5.5 v@1 mhz to 16 mhz ls (low-speed main) mode: 1.8 v v dd 5.5 v@1 mhz to 8 mhz hs (high-speed main) mode only: 2.7 v v dd 5.5 v@1 mhz to 24 mhz 2.4 v v dd 5.5 v@1 mhz to 16 mhz high-speed on-chip oscillator clock accuracy r5f102 products, 1.8 v v dd 5.5 v: 1.0%@ t a = -20 to +85 c 1.5%@ t a = -40 to -20 c r5f103 products, 1.8 v v dd 5.5 v: 5.0%@ t a = -40 to +85 c r5f102 products, 2.4 v v dd 5.5 v: 2.0%@ t a = +85 to +105 c 1.0%@ t a = -20 to +85 c 1.5%@ t a = -40 to -20 c serial array unit uart csi: f clk /2 (supporting 12 mbps), f clk /4 simplified i 2 c communication uart csi: f clk /4 simplified i 2 c communication voltage detector rise detection voltage: 1.88 v to 4.06 v (12 levels) fall detection voltage: 1.84 v to 3.98 v (12 levels) rise detection voltage: 2.61 v to 4.06 v (8 levels) fall detection voltage: 2.55 v to 3.98 v (8 levels) remark the electrical characteristics of the products g: industrial applications (t a = -40 to +105 c) are different from those of the products ?a: consumer applications, and d: industrial applications?. for details, refer to 3.1 to 3.10. rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 63 of 106 3.1 absolute maximum ratings absolute maximum ratings (t a = 25 c) parameter symbols conditions ratings unit supply voltage v dd ? 0.5 to + 6.5 v regc terminal input voltage note1 v iregc regc ? 0.3 to +2.8 and ?0.3 to v dd + 0.3 note 2 v input voltage v i1 other than p60, p61 ?0.3 to v dd + 0.3 note 3 v v i2 p60, p61 (n-ch open drain) ? 0.3 to 6.5 v output voltage v o ?0.3 to v dd + 0.3 note 3 v analog input voltage v ai 20, 24-pin products: ani0 to ani3, ani16 to ani22 30-pin products: ani0 to ani3, ani16 to ani19 ?0.3 to v dd + 0.3 and ?0.3 to av ref(+) +0.3 notes 3, 4 v output current, high i oh1 per pin other than p20 to p23 ?40 ma total of all pins all the terminals other than p20 to p23 ? 170 ma 20-, 24-pin products: p40 to p42 30-pin products: p00, p01, p40, p120 ?70 ma 20-, 24-pin products: p00 to p03 note 5 , p10 to p14 30-pin products: p10 to p17, p30, p31, p50, p51, p147 ? 100 ma i oh2 per pin p20 to p23 ? 0.5 ma total of all pins ?2 ma output current, low i ol1 per pin other than p20 to p23 40 ma total of all pins all the terminals other than p20 to p23 170 ma 20-, 24-pin products: p40 to p42 30-pin products: p00, p01, p40, p120 70 ma 20-, 24-pin products: p00 to p03 note 5 , p10 to p14, p60, p61 30-pin products: p10 to p17, p30, p31, p50, p51, p60, p61, p147 100 ma i ol2 per pin p20 to p23 1 ma total of all pins 5 ma operating ambient temperature t a ? 40 to +105 c storage temperature t stg ? 65 to +150 c notes 1. 30-pin product only. 2. connect the regc pin to v ss via a capacitor (0.47 to 1 f). this value determines the absolute maximum rating of the regc pin. do not use it with voltage applied. 3. must be 6.5 v or lower. 4. do not exceed av ref (+) + 0.3 v in case of a/d conversion target pin . 5. 24-pin products only. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings ar e rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remarks 1. unless specified otherwise, the characteristics of alter nate-function pins are the sa me as those of the port pins. 2. av ref (+): + side reference voltage of the a/d converter. 3. v ss : reference voltage rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 64 of 106 3.2 oscillator characteristics 3.2.1 x1 oscillator characteristics (t a = ? 40 to +105 c, 2.4 v v dd v dd 5.5 v, v ss = 0 v) parameter resonator conditions min. typ. max. unit x1 clock oscillation frequency (f x ) note ceramic resonator / crystal oscillator 2.7 v v dd 5.5 v 1.0 20.0 mhz 2.4 v v dd < 2.7 v 1.0 8.0 note indicates only permissible oscillator frequency ranges. refer to ac characteristics for instruction execution time. request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. caution since the cpu is started by the high-speed on-chip oscillator clock after a reset release, check the x1 clock oscillation stabilization time using the oscillation stabilization time counter status register (ostc) by the user. determine the oscilla tion stabilization time of the ostc register and the oscillation stabilization time select register (osts) after sufficiently evaluati ng the oscillation stabilization time with the resonator to be used. remark when using the x1 oscillator, refer to 5.4 system clock oscillator in the rl78/g12 user?s manual hardware. 3.2.2 on-chip oscillator characteristics (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) oscillators parameters conditions min. typ. max. unit high-speed on-chip oscillator clock frequency notes 1, 2 f ih 1 24 mhz high-speed on-chip oscillator clock frequency accuracy r5f102 products t a = ? 20 to +85 c -1.0 +1.0 % t a = ? 40 to ?20 c -1.5 +1.5 % t a = +85 to +105 c -2.0 +2.0 % low-speed on-chip oscillator clock frequency f il 15 khz low-speed on-chip oscillator clock frequency accuracy -15 +15 % notes 1. high-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000c2h) and bits 0 to 2 of hocodiv register. 2. this only indicates the oscillator characteristics. refe r to ac characteristics for instruction execution time. rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 65 of 106 3.3 dc characteristics 3.3.1 pin characteristics (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) (1/4) parameter symbol conditions min. typ. max. unit output current, high note 1 i oh1 20-, 24-pin products: per pin for p00 to p03 note 4 , p10 to p14, p40 to p42 30-pin products: per pin for p00, p01, p10 to p17, p30, p31, p40, p50, p51, p120, p147 ? 3.0 note 2 ma 20-, 24-pin products: total of p40 to p42 30-pin products: total of p00, p01, p40, p120 (when duty 70% note 3 ) 4.0 v v dd 5.5 v ? 9.0 ma 2.7 v v dd < 4.0 v ? 6.0 ma 2.4 v v dd < 2.7 v ? 4.5 ma 20-, 24-pin products: total of p00 to p03 note 4 , p10 to p14 30-pin products: total of p10 to p17, p30, p31, p50, p51, p147 (when duty 70% note 3 ) 4.0 v v dd 5.5 v ? 27.0 ma 2.7 v v dd < 4.0 v ? 18.0 ma 2.4 v v dd < 2.7 v ? 10.0 ma total of all pins (when duty 70% note 3 ) ? 36.0 ma i oh2 per pin for p20 to p23 ? 0.1 ma total of all pins ? 0.4 ma notes 1 . value of current at which the device operatio n is guaranteed even if the cu rrent flows from the v dd pin to an output pin. 2. however, do not exceed the total current value. 3. the output current value under conditions where the duty factor 70%. if duty factor > 70%: the output current value can be calculated with the following expression (where n represents the duty factor as a percentage). ? total output current of pins = (i oh 0.7)/(n 0.01) rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 66 of 106 (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) (2/4) parameter symbol conditions min. typ. max. unit output current, low note 1 i ol1 20-, 24-pin products: per pin for p00 to p03 note 4 , p10 to p14, p40 to p42 30-pin products: per pin for p00, p01, p10 to p17, p30, p31, p40, p50, p51, p120, p147 8.5 note 2 ma per pin for p60, p61 15.0 note 2 ma 20-, 24-pin products: total of p40 to p42 30-pin products: total of p00, p01, p40, p120 (when duty 70% note 3 ) 4.0 v v dd 5.5 v 25.5 ma 2.7 v v dd < 4.0 v 9.0 ma 2.4 v v dd < 2.7 v 1.8 ma 20-, 24-pin products: total of p00 to p03 note 4 , p10 to p14, p60, p61 30-pin products: total of p10 to p17, p30, p31, p50, p51, p60, p61, p147 (when duty 70% note 3 ) 4.0 v v dd 5.5 v 40.0 ma 2.7 v v dd < 4.0 v 27.0 ma 2.4 v v dd < 2.7 v 5.4 ma total of all pins (when duty 70% note 3 ) 65.5 ma i ol2 per pin for p20 to p23 0.4 ma total of all pins 1.6 ma notes 1 . value of current at which the devic e operation is guaranteed even if the current flow s from an output pin to the v ss pin. 2. however, do not exceed the total current value. 3. the output current value under conditions where the duty factor 70%. if duty factor > 70%: the output current value can be calculated with the following expression (where n represents the duty factor as a percentage). ? total output current of pins = (i ol 0.7)/(n 0.01) rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 67 of 106 (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) (3/4) parameter symbol conditions min. typ. max. unit input voltage, high v ih1 normal input buffer 20-, 24-pin products: p00 to p03 note 2 , p10 to p14, p40 to p42 30-pin products: p00, p01, p10 to p17, p30, p31, p40, p50, p51, p120, p147 0.8v dd v dd v v ih2 ttl input buffer 20-, 24-pin products: p10, p11 30-pin products: p01, p10, p11, p13 to p17 4.0 v v dd 5.5 v 2.2 v dd v 3.3 v v dd < 4.0 v 2.0 v dd v 2.4 v v dd < 3.3 v 1.5 v dd v v ih3 normal input buffer p20 to p23 0.7v dd v dd v v ih4 p60, p61 0.7v dd 6.0 v v ih5 p121, p122, p125 note 1 , p137, exclk, reset 0.8v dd v dd v input voltage, low v il1 normal input buffer 20-, 24-pin products: p00 to p03 note 2 , p10 to p14, p40 to p42 30-pin products: p00, p01, p10 to p17, p30, p31, p40, p50, p51, p120, p147 0 0.2v dd v v il2 ttl input buffer 20-, 24-pin products: p10, p11 30-pin products: p01, p10, p11, p13 to p17 4.0 v v dd 5.5 v 0 0.8 v 3.3 v v dd < 4.0 v 0 0.5 v 2.4 v v dd < 3.3 v 0 0.32 v v il3 p20 to p23 0 0.3v dd v v il4 p60, p61 0 0.3v dd v v il5 p121, p122, p125 note 1 , p137, exclk, reset 0 0.2v dd v output voltage, high v oh1 20-, 24-pin products: p00 to p03 note 2 , p10 to p14, p40 to p42 30-pin products: p00, p01, p10 to p17, p30, p31, p40, p50, p51, p120, p147 4.0 v v dd 5.5 v, i oh1 = ? 3.0 ma v dd ? 0.7 v 2.7 v v dd 5.5 v, i oh1 = ? 2.0 ma v dd ? 0.6 v 2.4 v v dd 5.5 v, i oh1 = ? 1.5 ma v dd ? 0.5 v v oh2 p20 to p23 i oh2 = ?100 a v dd ? 0.5 v notes 1. 20, 24-pin products only. 2. 24-pin products only. caution the maximum value of v ih of pins p10 to p12 and p41 for 20-pi n products, p01, p10 to p12, and p41 for 24-pin products, and p00, p10 to p15, p17, and p50 for 30-pin products is v dd even in n-ch open- drain mode. high level is not output in the n-ch open-drain mode. remark unless specified otherwise, the characteristics of alte rnate-function pins are the same as those of the port pins. rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 68 of 106 (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) (4/4) parameter symbol conditions min. typ. max. unit output voltage, low v ol1 20-, 24-pin products: p00 to p03 note , p10 to p14, p40 to p42 30-pin products: p00, p01, p10 to p17, p30, p31, p40, p50, p51, p120, p147 4.0 v v dd 5.5 v, i ol1 = 8.5 ma 0.7 v 2.7 v v dd 5.5 v, i ol1 = 3.0 ma 0.6 v 2.7 v v dd 5.5 v, i ol1 = 1.5 ma 0.4 v 2.4 v v dd 5.5 v, i ol1 = 0.6 ma 0.4 v v ol2 p20 to p23 i ol2 = 400 a 0.4 v v ol3 p60, p61 4.0 v v dd 5.5 v, i ol1 = 15.0 ma 2.0 v 4.0 v v dd 5.5 v, i ol1 = 5.0 ma 0.4 v 2.7 v v dd 5.5 v, i ol1 = 3.0 ma 0.4 v 2.4 v v dd 5.5 v, i ol1 = 2.0 ma 0.4 v input leakage current, high i lih1 other than p121, p122 v i = v dd 1 a i lih2 p121, p122 (x1, x2/exclk) v i = v dd input port or external clock input 1 a when resonator connected 10 a input leakage current, low i lil1 other than p121, p122 v i = v ss ?1 a i lil2 p121, p122 (x1, x2/exclk) v i = v ss input port or external clock input ?1 a when resonator connected ?10 a on-chip pull-up resistance r u 20-, 24-pin products: p00 to p03 note , p10 to p14, p40 to p42, p125, reset 30-pin products: p00, p01, p10 to p17, p30, p31, p40, p50, p51, p120, p147 v i = v ss , input port 10 20 100 k note 24-pin products only. remark unless specified otherwise, the characteristics of alte rnate-function pins are the same as those of the port pins. rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 69 of 106 3.3.2 supply current characteristics (1) 20-, 24-pin products (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit supply current note 1 i dd1 operating mode hs (high-speed main) mode note 4 f ih = 24 mhz note 3 basic operation v dd = 5.0 v 1.5 ma v dd = 3.0 v 1.5 normal operation v dd = 5.0 v 3.3 5.3 ma v dd = 3.0 v 3.3 5.3 f ih = 16 mhz note 3 v dd = 5.0 v 2.5 3.9 ma v dd = 3.0 v 2.5 3.9 f mx = 20 mhz note 2 , v dd = 5.0 v square wave input 2.8 4.7 ma resonator connection 3.0 4.8 f mx = 20 mhz note 2 , v dd = 3.0 v square wave input 2.8 4.7 ma resonator connection 3.0 4.8 f mx = 10 mhz note 2 , v dd = 5.0 v square wave input 1.8 2.8 ma resonator connection 1.8 2.8 f mx = 10 mhz note 2 , v dd = 3.0 v square wave input 1.8 2.8 ma resonator connection 1.8 2.8 notes 1. total current flowing into v dd , including the input leakage current flow ing when the level of the input pin is fixed to v dd or v ss . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d converter, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. when high-speed on-chip oscillator clock is stopped. 3. when high-speed system clock is stopped 4. relationship between operation voltage width, oper ation frequency of cpu and operation mode is as follows. hs(high speed main) mode: v dd = 2.7 v to 5.5 v @1 mhz to 24 mhz v dd = 2.4 v to 5.5 v @1 mhz to 16 mhz remarks 1. f mx : high-speed system clock frequency (x1 clock oscilla tion frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. temperature condition of the typ. value is t a = 25 c. rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 70 of 106 (1) 20-, 24-pin products (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit supply current note 1 i dd2 note 2 halt mode hs (high-speed main) mode note 6 f ih = 24 mhz note 4 v dd = 5.0 v 440 2230 a v dd = 3.0 v 440 2230 f ih = 16 mhz note 4 v dd = 5.0 v 400 1650 a v dd = 3.0 v 400 1650 f mx = 20 mhz note 3 , v dd = 5.0 v square wave input 280 1900 a resonator connection 450 2000 f mx = 20 mhz note 3 , v dd = 3.0 v square wave input 280 1900 a resonator connection 450 2000 f mx = 10 mhz note 3 , v dd = 5.0 v square wave input 190 1010 a resonator connection 260 1090 f mx = 10 mhz note 3 , v dd = 3.0 v square wave input 190 1010 a resonator connection 260 1090 i dd3 note 5 stop mode t a = ?40 c 0.19 0.50 a t a = +25 c 0.24 0.50 t a = +50 c 0.32 0.80 t a = +70 c 0.48 1.20 t a = +85 c 0.74 2.20 t a = +105 c 1.50 10.20 notes 1. total current flowing into v dd , including the input leakage current flow ing when the level of the input pin is fixed to v dd or v ss . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d converter, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. during halt instruction execution by flash memory. 3. when high-speed on-chip oscillator clock is stopped. 4. when high-speed system clock is stopped. 5. not including the current flowing into the 12-bit interval timer and watchdog timer. 6. relationship between operation voltage width, operation frequency of cpu and operation mode is as follows. hs (high speed main) mode: v dd = 2.7 v to 5.5 v @1 mhz to 24 mhz v dd = 2.4 v to 5.5 v @1 mhz to 16 mhz remarks 1. f mx : high-speed system clock frequency (x1 clock oscilla tion frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. except temperature conditi on of the typ. value is t a = 25 c, other than stop mode rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 71 of 106 (2) 30-pin products (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit supply current note 1 i dd1 operating mode hs (high-speed main) mode note 4 f ih = 24 mhz note 3 basic operation v dd = 5.0 v 1.5 ma v dd = 3.0 v 1.5 normal operation v dd = 5.0 v 3.7 5.8 ma v dd = 3.0 v 3.7 5.8 f ih = 16 mhz note 3 v dd = 5.0 v 2.7 4.2 ma v dd = 3.0 v 2.7 4.2 f mx = 20 mhz note 2 , v dd = 5.0 v square wave input 3.0 4.9 ma resonator connection 3.2 5.0 f mx = 20 mhz note 2 , v dd = 3.0 v square wave input 3.0 4.9 ma resonator connection 3.2 5.0 f mx = 10 mhz note 2 , v dd = 5.0 v square wave input 1.9 2.9 ma resonator connection 1.9 2.9 f mx = 10 mhz note 2 , v dd = 3.0 v square wave input 1.9 2.9 ma resonator connection 1.9 2.9 notes 1. total current flowing into v dd , including the input leakage current flowin g when the level of the input pin is fixed to v dd or v ss . the values below the max. column include the peripheral operation current. however, not including the cu rrent flowing into the a/d converter, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. when high-speed on-chip oscillator clock is stopped. 3. when high-speed system clock is stopped 4. relationship between operation voltage width, operation frequency of cpu and operation mode is as follows. hs(high speed main) mode: v dd = 2.7 v to 5.5 v @1 mhz to 24 mhz v dd = 2.4 v to 5.5 v @1 mhz to 16 mhz remarks 1. f mx : high-speed system clock frequency (x1 clock oscilla tion frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. temperature condition of the typ. value is t a = 25 c. rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 72 of 106 (2) 30-pin products (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit supply current note 1 i dd2 note 2 halt mode hs (high-speed main) mode note 6 f ih = 24 mhz note 4 v dd = 5.0 v 440 2300 a v dd = 3.0 v 440 2300 f ih = 16 mhz note 4 v dd = 5.0 v 400 1700 a v dd = 3.0 v 400 1700 f mx = 20 mhz note 3 , v dd = 5.0 v square wave input 280 1900 a resonator connection 450 2000 f mx = 20 mhz note 3 , v dd = 3.0 v square wave input 280 1900 a resonator connection 450 2000 f mx = 10 mhz note 3 , v dd = 5.0 v square wave input 190 1020 a resonator connection 260 1100 f mx = 10 mhz note 3 , v dd = 3.0 v square wave input 190 1020 a resonator connection 260 1100 i dd3 note 5 stop mode t a = ?40 c 0.18 0.50 a t a = +25 c 0.23 0.50 t a = +50 c 0.30 1.10 t a = +70 c 0.46 1.90 t a = +85 c 0.75 3.30 t a = +105 c 2.94 15.30 notes 1. total current flowing into v dd , including the input leakage current flowin g when the level of the input pin is fixed to v dd or v ss . the values below the max. column include the peripheral operation current. however, not including the cu rrent flowing into the a/d converter, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. during halt instruction execution by flash memory. 3. when high-speed on-chip oscillator clock is stopped. 4. when high-speed system clock is stopped. 5. not including the current flowing into the 12-bit interval timer and watchdog timer. 6. relationship between operation voltage width, operation frequency of cpu and operation mode is as follows. hs (high speed main) mode: v dd = 2.7 v to 5.5 v @1 mhz to 24 mhz v dd = 2.4 v to 5.5 v @1 mhz to 16 mhz remarks 1. f mx : high-speed system clock frequency (x1 clock oscilla tion frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. except stop mode, temperature c ondition of the typ. value is t a = 25 c. rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 73 of 106 (3) peripheral functions (common to all products) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit low-speed onchip oscillator operating current i fil note 1 0.20 a 12-bit interval timer operating current i tmka notes 1, 2, 3 0.02 a watchdog timer operating current i wdt notes 1, 2, 4 f il = 15 khz 0.22 a a/d converter operating current i adc notes 1, 5 when conversion at maximum speed normal mode, av refp = v dd = 5.0 v 1.30 1.70 ma low voltage mode, av refp = v dd = 3.0 v 0.50 0.70 ma a/d converter reference voltage operating current i adref note 1 75.0 a temperature sensor operating current i tmps note 1 75.0 a lvd operating current i lvd notes 1, 6 0.08 a self-programming operating current i fsp notes 1, 8 2.00 12.20 ma bgo operating current i bgo notes 1, 7 2.00 12.20 ma snooze operating current i snoz note 1 adc operation the mode is performed note 9 0.50 1.10 ma the a/d conversion operations are performed, low voltage mode, av refp = v dd = 3.0 v 1.20 2.04 ma csi/uart operation 0.70 1.54 ma notes 1. current flowing to the v dd. 2. when high speed on-chip oscillator and high-speed system clock are stopped. 3. current flowing only to the 12-bit interval timer (e xcluding the operating current of the low-speed on-chip oscillator). the current value of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 , and i fil and i tmka when the 12-bit interval timer operates. 4. current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). the current value of the rl78 mi crocontrollers is the sum of i dd1 , i dd2 or i dd3 and i wdt when the watchdog timer operates. 5. current flowing only to the a/d converter. the current value of the rl78 microcontrollers is the sum of i dd1 or i dd2 and i adc when the a/d converter operates in an operation mode or the halt mode. 6. current flowing only to the lvd circuit. the current value of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i lvd when the lvd circuit operates. 7. current flowing only during data flash rewrite. 8. current flowing only during self programming. 9. for shift time to the snooze mode, see 17.3.3 snooze mode in the rl 78/g12 user?s manual hardware . remarks 1. f il : low-speed on-chip oscillator clock frequency 2. temperature condition of the typ. value is t a = 25 c rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 74 of 106 3.4 ac characteristics (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit instruction cycle (minimum instruction execution time) t cy main system clock (f main ) operation hs (high- speed main) mode 2.7 v v dd 5.5 v 0.04167 1 s 2.4 v v dd < 2.7 v 0.0625 1 s during self programming hs (high- speed main) mode 2.7 v v dd 5.5 v 0.04167 1 s 2.4 v v dd < 2.7 v 0.0625 1 s external main system clock frequency f ex 2.7 v v dd 5.5 v 1.0 20.0 mhz 2.4 v v dd < 2.7 v 1.0 16.0 mhz external main system clock input high-level width, low- level width t exh , t exl 2.7 v v dd 5.5 v 24 ns 2.4 v v dd < 2.7 v 30 ns ti00 to ti07 input high-level width, low-level width t tih , t til 1/f mck + 10 ns to00 to to07 output frequency f to 4.0 v v dd 5.5 v 12 mhz 2.7 v v dd < 4.0 v 8 mhz 2.4 v v dd < 2.7 v 4 mhz pclbuz0, or pclbuz1 output frequency f pcl 4.0 v v dd 5.5 v 16 mhz 2.7 v v dd < 4.0 v 8 mhz 2.4 v v dd < 2.7 v 4 mhz intp0 to intp5 input high- level width, low-level width t inth , t intl 1 s kr0 to kr9 input available width t kr 250 ns reset low-level width t rsl 10 s remark f mck : timer array unit operation clock frequency (operation clock to be set by the timer clock select register 0 (tps0) and the cks0n bit of timer mode register 0n (tmr0n). n: channel number (n = 0 to 7)) rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 75 of 106 minimum instruction execution time during main system clock operation t cy vs v dd (hs (high-speed main) mode) when the high-speed on-chip oscillator clock is selected during self programming when high-speed system clock is selected cycle time t cy [s] supply voltage v dd [v] 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 0.01 2.4 0.04167 0.0625 ac timing test point v ih /v oh v il /v ol test points v ih /v oh v il /v ol external main system clock timing exclk 1/f ex t exl t exh rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 76 of 106 ti/to timing ti00 to ti07 t til t tih to00 to to07 1/f to interrupt request input timing intp0 to intp5 t intl t inth key interrupt input timing kr0 to kr9 t kr reset input timing reset t rsl rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 77 of 106 3.5 peripheral functions characteristics ac timing test point v ih /v oh v il /v ol test points v ih /v oh v il /v ol 3.5.1 serial array unit (1) during communication at same potential (uart mode) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. transfer rate note 1 f mck /12 bps theoretical value of the maximum transfer rate f clk = f mck note2 2.0 mbps notes 1. transfer rate in the snooze mode is 4800 bps only. 2. the maximum operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main ) mode: 24 mhz (2.7 v v dd 5.5 v) 16 mhz (2.4 v v dd 5.5 v) caution select the normal input buffer for the rxdq pin and the normal output mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). uart mode connection diagram (during communication at same potential) rl78 microcontroller txdq rxdq rx tx user's device uart mode bit width (during communication at same potential) (reference) txdq rxdq baud rate error tolerance high-/low-bit width 1/transfer rate remarks 1. q: uart number (q = 0 to 2), g: pim, pom number (g = 0, 1) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the serial clock se lect register m (spsm) and the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10, 11)) rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 78 of 106 (2) during communication at same pot ential (csi mode) (master mode , sckp... internal clock output) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. sckp cycle time t kcy1 t kcy1 4/f clk 2.7 v v dd 5.5 v 334 ns 2.4 v v dd 5.5 v 500 ns sckp high-/low-level width t kh1 , t kl1 4.0 v v dd 5.5 v t kcy1 /2? 24 ns 2.7 v v dd 5.5 v t kcy1 /2? 36 ns 2.4 v v dd 5.5 v t kcy1 /2? 76 ns sip setup time (to sckp ) note 1 t sik1 4.0 v v dd 5.5 v 66 ns 2.7 v v dd 5.5 v 66 ns 2.4 v v dd 5.5 v 113 ns sip hold time (from sckp ) note 2 t ksi1 38 ns delay time from sckp to sop output note 3 t kso1 c = 30 pf note4 50 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for the sip pin and the normal output mode for the sop and sckp pins by using port input mode register 1 (pim1) and port output mode registers 0, 1, 4 (pom0, pom1, pom4). remarks 1. p: csi number (p = 00, 01, 11, 20), m: unit number (m = 0, 1), n: channel number (n = 0, 1, 3) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the serial clock sele ct register m (spsm) and the cksmn bit of serial mode register mn (smrmn). m: unit number (m = 0, 1), n: channel number (n = 0, 1, 3)) rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 79 of 106 (3) during communication at same potential (csi mode) (slave mode, sckp... external clock input) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. sckp cycle time note4 t kcy2 4.0 v v dd 5.5 v 20 mhz < f mck 16/f mck ns f mck 20 mhz 12/f mck ns 2.7 v v dd 5.5 v 16 mhz < f mck 16/f mck ns f mck 16 mhz 12/f mck ns 2.4 v v dd 5.5 v 12/f mck and 1000 ns sckp high-/low-level width t kh2 , t kl2 4.0 v v dd 5.5 v t kcy2 /2? 14 ns 2.7 v v dd 5.5 v t kcy2 /2? 16 ns 2.4 v v dd 5.5 v t kcy2 /2? 36 ns sip setup time (to sckp ) note 1 t sik2 2.7 v v dd 5.5 v 1/f mck + 40 ns 2.4 v v dd 5.5 v 1/f mck + 60 ns sip hold time (from sckp ) note 2 t ksi2 1/f mck + 62 ns delay time from sckp to sop output note 3 t kso2 c = 30 pf note4 2.7 v v dd 5.5 v 2/f mck + 66 ns 2.4 v v dd 5.5 v 2/f mck + 113 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitanc e of the sop output lines. 5. transfer rate in the snooze mode: max. 1 mbps caution select the normal input buffer for the sip and sckp pins and the normal output mode for the sop pin by using port input mode register 1 (pim1) and port output mode registers 0, 1, 4 (pom0, pom1, pom4). csi mode connection diagram (duri ng communication at same potential) rl78 microcontroller sckp sop sck si user's device sip so rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 80 of 106 csi mode serial transfer timing (dur ing communication at same potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) si p sop t kcy1, 2 t kl1, 2 t kh1, 2 t si k1 , 2 t ksi1, 2 t kso1, 2 sckp input data output data csi mode serial transfer timing (dur ing communication at same potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) si p sop t kcy1, 2 t kh1, 2 t kl1, 2 t si k1 , 2 t ksi1, 2 t kso1, 2 sckp input data out put dat a remarks 1. p: csi number (p = 00, 01, 11, 20), m: unit number (m = 0, 1), n: channel number (n = 0, 1, 3) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the serial clock se lect register m (spsm) and the cksmn bit of serial mode register mn (smrmn). m: unit number (m = 0,1), n: channel num ber (n = 0, 1, 3)) rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 81 of 106 (4) during communication at same potential (simplified i 2 c mode) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. sclr clock frequency f scl c b = 100 pf, r b = 3 k 100 note 1 khz hold time when sclr = ?l? t low c b = 100 pf, r b = 3 k 4600 ns hold time when sclr = ?h? t high c b = 100 pf, r b = 3 k 4600 ns data setup time (reception) t su:dat c b = 100 pf, r b = 3 k 1/f mck + 580 note 2 ns data hold time (transmission) t hd:dat c b = 100 pf, r b = 3 k 0 1420 ns notes 1. the value must also be equal to or less than f mck /4. 2. set t su:dat so that it will not exceed the hold ti me when sclr = "l" or sclr = "h". caution select the n-ch open drain output (v dd tolerance) mode for sdar by using port output mode register h (pomh). simplified i 2 c mode connection diagram (during communication at same potential) rl78 microcontroller sdar sclr sda scl user's device v dd r b simplified i 2 c mode serial transfer timing (during communication at same potential) sdar t low t high t hd:dat sclr t su:dat 1/f scl remarks 1. r b [ ]:communication line (sdar) pull-up resistance c b [f]: communication line (sclr, sdar) load capacitance 2. r: iic number (r = 00, 01, 11, 20), h: = pom number (h = 0, 1, 4, 5) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the serial clock select register m (spsm) and the cksmn bit of serial mode register mn (smrmn). m: unit number (m = 0, 1), n: channel number (0, 1, 3)) rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 82 of 106 (5) communication at different potential (1.8 v, 2.5 v, 3 v) (uart mode) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. transfer rate note4 reception 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v f mck /12 note 1 bps theoretical value of the maximum transfer rate f mck = f clk note 2 2.0 mbps 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v f mck /12 note 1 bps theoretical value of the maximum transfer rate f mck = f clk note 2 2.0 mbps 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v f mck /12 note 1 bps theoretical value of the maximum transfer rate f mck = f clk note 2 2.0 mbps transmission 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v note 3 bps theoretical value of the maximum transfer rate c b = 50 pf, r b = 1.4 k , v b = 2.7 v 2.0 note 4 mbps 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, note 5 bps theoretical value of the maximum transfer rate c b = 50 pf, r b = 2.7 k , v b = 2.3 v 1.2 note 6 mbps 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v notes 2, 7 bps theoretical value of the maximum transfer rate c b = 50 pf, r b = 5.5 k , v b = 1.6 v 0.43 note 8 mbps notes 1. transfer rate in the snooze mode is 4800 bps only. 2. the maximum operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main ) mode: 24 mhz (2.7 v v dd 5.5 v) 16 mhz (2.4 v v dd 5.5 v) 3. the smaller maximum transfer rate derived by using f mck /12 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 4.0 v v dd 5.5 v and 2.7 v v b 4.0 v maximum transfer rate = 1 [bps] { ?c b r b ln (1 ? 2.2 v b )} 3 1 transfer rate 2 ? { ?c b r b ln (1 ? 2.2 v b )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical value of the relative difference betwe en the transmission and reception sides. rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 83 of 106 4. this value as an example is calculated when the condi tions described in the ?conditions? column are met. refer to note 3 above to calculate the maximum transfer rate under conditions of the customer. 5. the smaller maximum transfer rate derived by using f mck /12 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.7 v v dd < 4.0 v and 2.3 v v b 2.7 v maximum transfer rate = 1 [bps] { ?c b r b ln (1 ? 2.0 v b )} 3 1 transfer rate 2 ? { ?c b r b ln (1 ? 2.0 v b )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical value of the relative difference betwe en the transmission and reception sides. 6. this value as an example is calculated when the condi tions described in the ?conditions? column are met. refer to note 5 above to calculate the maximum transfer rate under conditions of the customer. 7. the smaller maximum transfer rate derived by using f mck /12 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v maximum transfer rate = 1 [bps] { ?c b r b ln (1 ? 1.5 v b )} 3 1 transfer rate 2 ? { ?c b r b ln (1 ? 1.5 v b )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical value of the relative difference betwe en the transmission and reception sides. 8. this value as an example is calculated when the condi tions described in the ?conditions? column are met. refer to note 7 above to calculate the maximum transfer rate under conditions of the customer. caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance) mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 84 of 106 uart mode connection diagram (during communication at different potential) rl78 microcontroller txdq rxdq rx tx user's device v b r b uart mode bit width (during communication at different potential) (reference) txdq rxdq baud rate error tolerance high-/low-bit width 1/transfer rate baud rate error tolerance high-bit width low-bit width 1/transfer rate remarks 1. r b [ ]: communication line (txdq) pull-up resistance, c b [f]: communication line (txdq) load capacitance, v b [v]: communication line voltage 2. q: uart number (q = 0 to 2), g: pim and pom number (g = 0, 1) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the serial clock sele ct register m (spsm) and the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10, 11)) 4. uart0 of the 20- and 24-pin products supports communication at different potential only when the peripheral i/o redirection function is not used. rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 85 of 106 (6) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output) (1/3) (t a = ? 40 to +105 c, 2.4 v v dd v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. sckp cycle time t kcy1 t kcy1 4/f clk 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 600 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 1000 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 2300 ns sckp high-level width t kh1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k t kcy1 /2 ? 150 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 ? 340 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k t kcy1 /2 ? 916 ns sckp low-level width t kl1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k t kcy1 /2 ? 24 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 ? 36 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k t kcy1 /2 ? 100 ns cautions 1. select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register 1 (pim1) and port output mode register 1 (pom1). for v ih and v il , see the dc characteristics with ttl input buffer selected. 2. csi01 and csi11 cannot communicate at different potential. remarks 1. r b [ ]: communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage 2. p: csi number (p = 00, 20) rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 86 of 106 (6) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output) (2/3) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. sip setup time (to sckp ) note t sik1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 162 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 354 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 958 ns sip hold time (from sckp ) note t ksi1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 38 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 38 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 38 ns delay time from sckp to sop output note t kso1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 200 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 390 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 966 ns note when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. ( cautions and remarks are listed on the next page.) rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 87 of 106 (6) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output) (3/3) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. sip setup time (to sckp ) note t sik1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 88 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 88 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 220 ns sip hold time (from sckp ) note t ksi1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 38 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 38 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 38 ns delay time from sckp to sop output note t kso1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 50 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 50 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 50 ns note when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. cautions 1. select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register 1 (pim1) and port output mode register 1 (pom1). for v ih and v il , see the dc characteristics with ttl input buffer selected. 2. csi01 and csi11 cannot communicate at different potential. remarks 1. r b [ ]: communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage 2. p: csi number (p = 00, 20), m: unit numbe r (m = 0, 1), n: channel number (n = 0) csi mode connection diagram (during communication at different potential) v b r b sckp sop sck si user's device sip so v b r b rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 88 of 106 csi mode serial transfer timing (master mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1) input data output data sip sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sckp csi mode serial transfer timing (master mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sip sop sckp input data output data remark p: csi number (p = 00, 20), m: unit numbe r (m = 0, 1), n: channel number (n = 0) rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 89 of 106 (7) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (slave mode, sckp... external clock input) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. sckp cycle time note 1 t kcy2 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v 20 mhz < f mck 24 mhz 24/f mck ns 8 mhz < f mck 20 mhz 20/f mck ns 4 mhz < f mck 8 mhz 16/f mck ns f mck 4 mhz 12/f mck ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v 20 mhz < f mck 24 mhz 32/f mck ns 16 mhz < f mck 20 mhz 28/f mck ns 8 mhz < f mck 16 mhz 24/f mck ns 4 mhz < f mck 8 mhz 16/f mck ns f mck 4 mhz 12/f mck ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v 20 mhz < f mck 24 mhz 72/f mck ns 16 mhz < f mck 20 mhz 64/f mck ns 8 mhz < f mck 16 mhz 52/f mck ns 4 mhz < f mck 8 mhz 32/f mck ns f mck 4 mhz 20/f mck ns sckp high-/low-level width t kh2 , t kl2 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v t kcy2 /2 ? 24 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v t kcy2 /2 ? 36 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v t kcy2 /2 ? 100 ns sip setup time (to sckp ) note 2 t sik2 4.0 v v dd 5.5 v, 2.7 v v dd 4.0 v 1/f mck + 40 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v 1/f mck + 40 ns 2.4 v v dd < 3.3 v, 1.6 v v dd 2.0 v 1/f mck + 60 ns sip hold time (from sckp ) note 3 t ksi2 1/f mck + 62 ns delay time from sckp to sop output note 4 t kso2 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 2/f mck + 240 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 2/f mck + 428 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 2/f mck + 1146 ns notes 1. transfer rate in the snooze mode: max. 1 mbps 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. cautions 1. select the ttl input buffer for the sip and sckp pins and the n-ch open drain output (v dd tolerance) mode for the sop pin by using port input mode register 1 (pim1) and port output mode register 1 (pom1). for v ih and v il , see the dc characteristics with ttl input buffer selected. 2. csi01 and csi11 cannot communicate at different potential. rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 90 of 106 csi mode connection diagram (during communication at different potential) rl78 microcontroller sop sck si user's device sip so v b r b sckp rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 91 of 106 csi mode serial transfer timing (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) input data output data sip sop t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2 sckp remark p: csi number (p = 00, 20), m: unit numbe r (m = 0, 1), n: channel number (n = 0) rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 92 of 106 (8) communication at different potential (1.8 v, 2.5 v, 3 v) (simplified i 2 c mode) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. sclr clock frequency f scl 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 100 note1 khz 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 100 note1 khz 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 100 pf, r b = 5.5 k 100 note1 khz hold time when sclr = ?l? t low 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 4600 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 4600 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 100 pf, r b = 5.5 k 4650 ns hold time when sclr = ?h? t high 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 2700 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 2400 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 100 pf, r b = 5.5 k 1830 ns data setup time (reception) t su:dat 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 1/f mck + 760 note3 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 1/f mck + 760 note3 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 100 pf, r b = 5.5 k 1/f mck + 570 note3 ns data hold time (transmission) t hd:dat 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 0 1420 ns 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 0 1420 ns 2.4 v v dd < 3.3 v, 1.6 v v b 2.0 v, c b = 100 pf, r b = 5.5 k 0 1215 ns notes 1. the value must also be equal to or less than f mck /4. 2. set t su:dat so that it will not exceed the hold ti me when sclr = "l" or sclr = "h". cautions 1. select the ttl input buffer and the n-ch open drain output (v dd tolerance) mode for the sdar pin and the n-ch open drain output (v dd tolerance) mode for the sclr pin by using port input mode register 1 (pim1) and port output mode register 1 (pom1). for v ih and v il , see the dc characteristics with ttl input buffer selected. 2. iic01 and iic11 cannot communicate at different potential. ( remarks are listed on the next page.) rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 93 of 106 simplified i 2 c mode connection diagram (during communication at different potential) sdar sclr sda scl user's device v b r b v b r b rl78 microcontroller simplified i 2 c mode serial transfer timing (during communication at different potential) sdar t low t high t hd : dat sclr t su : dat 1/f scl remarks 1. r b [ ]: communication line (sdar, sclr) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance, v b [v]: communication line voltage 2. r: iic number (r = 00, 20) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the serial clock select register m (spsm) and the cksmn bit of serial mode register mn (smrmn). m: unit number (m = 0,1), n: channel number (n = 0)) rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 94 of 106 3.5.2 serial interface iica (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode unit standard mode fast mode min. max. min. max. scla0 clock frequency f scl fast mode: f clk 3.5 mhz 0 400 khz normal mode: f clk 1 mhz 0 100 khz setup time of restart condition t su:sta 4.7 0.6 s hold time note 1 t hd:sta 4.0 0.6 s hold time when scla0 = ?l? t low 4.7 1.3 s hold time when scla0 = ?h? t high 4.0 0.6 s data setup time (reception) t su:dat 250 100 ns data hold time (transmission) note 2 t hd:dat 0 3.45 0 0.9 s setup time of stop condition t su:sto 4.0 0.6 s bus-free time t buf 4.7 1.3 s notes 1. the first clock pulse is generated after this per iod when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wa it state is inse rted in the ack (acknowledge) timing. caution only in the 30-pin products, the values in the above table are applied even when bit 2 (pior2) in the peripheral i/o redirection register (pior) is 1. at this time, the pin characteristics (i oh1 , i ol1 , v oh1 , v ol1 ) must satisfy the values in the redirect destination. remark the maximum value of c b (communication line capacitance) and the value of r b (communication line pull-up resistor) at that time in each mode are as follows. normal mode: c b = 400 pf, rb = 2.7 k fast mode: c b = 320 pf, rb = 1.1 k iica serial transfer timing t low t r t high t f t buf t hd:dat t su:dat t hd:sta t su:sta t hd:sta t su:sto scla0 sdaa0 stop condition start condition restart condition stop condition rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 95 of 106 3.6 analog characteristics 3.6.1 a/d converter characteristics classification of a/d converter characteristics input channel reference voltage reference voltage (+) = av refp reference voltage ( ? ) = av refm reference voltage (+) = v dd reference voltage ( ? ) = v ss reference voltage (+) = v bgr reference voltage ( ? ) = av refm ani0 to ani3 refer to 3.6.1 (1) . refer to 3.6.1 (3) . refer to 3.6.1 (4) . ani16 to ani22 refer to 3.6.1 (2) . internal reference voltage temperature sensor output voltage refer to 3.6.1 (1) . ? (1) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target pin: ani2, ani3, internal reference voltage, and temperature sensor output voltage (t a = ? 40 to +105 c, 2.4 v av refp v dd 5.5 v, v ss = 0 v, reference voltage (+) = av refp , reference voltage ( ? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution res 8 10 bit overall error note 1 ainl 10-bit resolution av refp = v dd note 3 1.2 3.5 lsb conversion time t conv 10-bit resolution target pin: ani2, ani3 3.6 v v dd 5.5 v 2.125 39 s 2.7 v v dd 5.5 v 3.1875 39 s 2.4 v v dd 5.5 v 17 39 s 10-bit resolution target pin: internal reference voltage, and temperature sensor output voltage (hs (high-speed main) mode) 3.6 v v dd 5.5 v 2.375 39 s 2.7 v v dd 5.5 v 3.5625 39 s 2.4 v v dd 5.5 v 17 39 s zero-scale error notes 1, 2 ezs 10-bit resolution av refp = v dd note 3 0.25 %fsr full-scale error notes 1, 2 efs 10-bit resolution av refp = v dd note 3 0.25 %fsr integral linearity error note 1 ile 10-bit resolution av refp = v dd note 3 2.5 lsb differential linearity error note 1 dle 10-bit resolution av refp = v dd note 3 1.5 lsb analog input voltage v ain ani2, ani3 0 av refp v internal reference voltage (hs (high-speed main) mode) v bgr note 4 v temperature sensor output voltage (hs (high-speed main) mode) v tmps25 note 4 v (notes are listed on the next page.) rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 96 of 106 notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. when av refp < v dd , the max. values are as follows. overall error: add 1.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add 0.05%fsr to the max. value when av refp = v dd . integral linearity error/ differential linearity error: add 0.5 lsb to the max. value when av refp = v dd . 4. refer to 3.6.2 temperature sensor/internal reference voltage characteristics . (2) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target pin: ani16 to ani22 (t a = ? 40 to +105 c, 2.4 v av refp v dd 5.5 v, v ss = 0 v, reference voltage (+) = av refp , reference voltage ( ? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 8 10 bit overall error note 1 ainl 10-bit resolution av refp = v dd note 3 1.2 5.0 lsb conversion time t conv 10-bit resolution target ani pin: ani16 to ani22 3.6 v v dd 5.5 v 2.125 39 s 2.7 v v dd 5.5 v 3.1875 39 s 2.4 v v dd 5.5 v 17 39 s zero-scale error notes 1, 2 ezs 10-bit resolution av refp = v dd note 3 0.35 %fsr full-scale error notes 1, 2 efs 10-bit resolution av refp = v dd note 3 0.35 %fsr integral linearity error note 1 ile 10-bit resolution av refp = v dd note 3 3.5 lsb differential linearity error note 1 dle 10-bit resolution av refp = v dd note 3 2.0 lsb analog input voltage v ain ani16 to ani22 0 av refp and v dd v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. when av refp v dd , the max. values are as follows. overall error: add 4.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add 0.20%fsr to the max. value when av refp = v dd . integral linearity error/ differential linearity error: add 2.0 lsb to the max. value when av refp = v dd . rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 97 of 106 (3) when reference voltage (+) = v dd (adrefp1 = 0, adrefp0 = 0), reference voltage ( ? ) = v ss (adrefm = 0), target pin: ani0 to ani3, ani16 to ani22, internal reference voltage, and temperature sensor output voltage (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v, reference voltage (+) = v dd , reference voltage ( ? ) = v ss ) parameter symbol conditions min. typ. max. unit resolution r es 8 10 bit overall error note 1 ainl 10-bit resolution 1.2 7.0 lsb conversion time t conv 10-bit resolution target pin: ani0 to ani3, ani16 to ani22 3.6 v v dd 5.5 v 2.125 39 s 2.7 v v dd 5.5 v 3.1875 39 s 2.4 v v dd 5.5 v 17 39 s conversion time t conv 10-bit resolution target pin: internal reference voltage, and temperature sensor output voltage (hs (high-speed main) mode) 3.6 v v dd 5.5 v 2.375 39 s 2.7 v v dd 5.5 v 3.5625 39 s 2.4 v v dd 5.5 v 17 39 s zero-scale error notes 1, 2 ezs 10-bit resolution 0.60 %fsr full-scale error notes 1, 2 efs 10-bit resolution 0.60 %fsr integral linearity error note 1 ile 10-bit resolution 4.0 lsb differential linearity error note 1 dle 10-bit resolution 2.0 lsb analog input voltage v ain ani0 to ani3, ani16 to ani22 0 v dd v internal reference voltage (hs (high-speed main) mode) v bgr note 3 v temperature sensor output voltage (hs (high-speed main) mode) v tmps25 note 3 v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. refer to 3.6.2 temperature sensor/internal reference voltage characteristics . rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 98 of 106 (4) when reference voltage (+) = internal reference voltage (adrefp1 = 1, adrefp0 = 0), reference voltage ( ? ) = av refm (adrefm = 1), target pin: ani0 , ani2, ani3, and ani16 to ani22 (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v, reference voltage (+) = v bgr note 3 , reference voltage ( ? ) = av refm note 4 = 0 v, hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit resolution r es 8 bit conversion time t conv 8-bit resolution 17 39 s zero-scale error notes 1, 2 ezs 8-bit resolution 0.60 %fsr integral linearity error note 1 ile 8-bit resolution 2.0 lsb differential linearity error note 1 dle 8-bit resolution 1.0 lsb analog input voltage v ain 0 v bgr note 3 v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. refer to 3.6.2 temperature sensor/internal reference voltage characteristics . 4. when reference voltage ( ? ) = v ss , the max. values are as follows. zero-scale error: add 0.35%fsr to the max. value when reference voltage ( ? ) = av refm . integral linearity error: add 0.5 lsb to the max. value when reference voltage ( ? ) = av refm . differential linearity error: add 0.2 lsb to the max. value when reference voltage ( ? ) = av refm . rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 99 of 106 3.6.2 temperature sensor/internal reference voltage characteristics (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v, hs (high-speed main) mode parameter symbol conditions min. typ. max. unit temperature sensor output voltage v tmps25 setting ads register = 80h, t a = +25 c 1.05 v internal reference voltage v bgr setting ads register = 81h 1.38 1.45 1.50 v temperature coefficient f vtmps temperature sensor output voltage that depends on the temperature ? 3.6 mv/ c operation stabilization wait time t amp 5 s 3.6.3 por circuit characteristics (t a = ? 40 to +105 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage v por power supply rise time 1.45 1.51 1.57 v v pdr power supply fall time 1.44 1.50 1.56 v minimum pulse width note t pw 300 s note minimum time required for a por reset when v dd exceeds below v pdr . this is also the minimum time required for a por reset from when v dd exceeds below 0.7 v to when v dd exceeds v por while stop mode is entered or the main system clock is stopped through setting bi t 0 (hiostop) and bit 7 (msto p) in the clock operation status control register (csc). t pw v por v pdr or 0.7 v supply voltage (v dd ) rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 100 of 106 3.6.4 lvd circuit characteristics lvd detection voltage of reset mode and interrupt mode (t a = ? 40 to +105 c, v pdr v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit detection supply voltage v lvd0 power supply rise time 3.90 4.06 4.22 v power supply fall time 3.83 3.98 4.13 v v lvd1 power supply rise time 3.60 3.75 3.90 v power supply fall time 3.53 3.67 3.81 v v lvd2 power supply rise time 3.01 3.13 3.25 v power supply fall time 2.94 3.06 3.18 v v lvd3 power supply rise time 2.90 3.02 3.14 v power supply fall time 2.85 2.96 3.07 v v lvd4 power supply rise time 2.81 2.92 3.03 v power supply fall time 2.75 2.86 2.97 v v lvd5 power supply rise time 2.70 2.81 2.92 v power supply fall time 2.64 2.75 2.86 v v lvd6 power supply rise time 2.61 2.71 2.81 v power supply fall time 2.55 2.65 2.75 v v lvd7 power supply rise time 2.51 2.61 2.71 v power supply fall time 2.45 2.55 2.65 v minimum pulse width t lw 300 s detection delay time 300 s rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 101 of 106 lvd detection voltage of interrupt & reset mode (t a = ? 40 to +105 c, v pdr v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit interrupt and reset mode v lvdd0 v poc2 , v poc1 , v poc1 = 0, 1, 1, falling reset voltage 2.64 2.75 2.86 v v lvdd1 lvis1, lvis0 = 1, 0 rising reset release voltage 2.81 2.92 3.03 v falling interrupt voltage 2.75 2.86 2.97 v v lvdd2 lvis1, lvis0 = 0, 1 rising reset release voltage 2.90 3.02 3.14 v falling interrupt voltage 2.85 2.96 3.07 v v lvdd3 lvis1, lvis0 = 0, 0 rising reset release voltage 3.90 4.06 4.22 v falling interrupt voltage 3.83 3.98 4.13 v 3.6.5 power supply voltage rising slope characteristics (t a = ? 40 to +105 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit power supply voltage rising slope s vdd 54 v/ms caution make sure to keep the internal reset state by the lvd circuit or an external reset until v dd reaches the operating voltage range shown in 3.4 ac characteristics. rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 102 of 106 3.7 data memory stop mode low supply voltage data retention characteristics (t a = ? 40 to +105 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.44 note 5.5 v note the value depends on the por detection voltage. when t he voltage drops, the data is retained before a por reset is affected, but data is not re tained when a por reset is affected. v dd v dddr stop instruction execution standby release signal (interrupt request) stop mode data retention mode operation mode 3.8 flash memory programming characteristics (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit system clock frequency f clk 1 24 mhz code flash memory rewritable times notes 1, 2, 3 c erwr retained for 20 years t a = 85c 1,000 times data flash memory rewritable times notes 1, 2, 3 retained for 1 year t a = 25c 1,000,000 retained for 5 years t a = 85c 100,000 retained for 20 years t a = 85c 10,000 notes 1. 1 erase + 1 write after the erase is regarded as 1 rewr ite. the retaining years are until next rewrite after the rewrite. 2. when using flash memory programmer and renesas electronics self programming library 3. these are the characteristics of t he flash memory and the results obtained from reliability testing by renesas electronics corporation. rl78/g12 3. electric al specifications (g: t a = ? 40 to +105 c) r01ds0193ej0200 rev.2.00 sep 06, 2013 page 103 of 106 3.9 dedicated flash memory programmer communication (uart) (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit transfer rate during serial programming 115,200 1,000,000 bps 3.10 timing of entry to flash memory programming modes (t a = ? 40 to +105 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit time to complete the communication for the initial setting after the external reset is released t suinit por and lvd reset are released before external release 100 ms time to release the external reset after the tool0 pin is set to the low level t su por and lvd reset are released before external release 10 s time to hold the tool0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) t hd por and lvd reset are released before external release 1 ms reset tool0 <1> <2> <3> t suinit t hd + software processing time 1-byte data for setting mode t su <4> <1> the low level is input to the tool0 pin. <2> the external reset is released (por and lvd reset must be released before the external reset is released.). <3> the tool0 pin is set to the high level. <4> setting of the flash memory programming mode by uart reception and complete the baud rate setting. remark t suinit : communication for the initial setting must be completed within 100 ms after the external reset is released during this period. t su : time to release the exte rnal reset after the tool0 pi n is set to the low level t hd : time to hold the tool0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) rl78/g12 4. package drawings r01ds0193ej0200 rev.2.00 sep 06, 2013 page 104 of 106 4. package drawings 4.1 20-pin products r5f1026aasp, r5f10269asp, r5f1026 8asp, r5f10267asp, r5f10266asp r5f1036aasp, r5f10369asp, r5f1036 8asp, r5f10367asp, r5f10366asp r5f1026adsp, r5f10269dsp, r5f10268dsp, r5f10267dsp, r5f10266dsp r5f1036adsp, r5f10369dsp, r5f10368dsp, r5f10367dsp, r5f10366dsp r5f1026agsp, r5f10269gsp, r5f102 68gsp, r5f10267gsp, r5f10266gsp r5f1036agsp, r5f10369gsp, r5f103 68gsp, r5f10367gsp, r5f10366gsp 2012 renesas electronics corporation. all rights reserved. jeita package code renesas code previous code mass (typ.) [g] p-lssop20-4.4x6.5-0.65 plsp0020jb-a p20ma-65-naa-1 0.1 20 1 10 detail of lead end item dimensions d e e a1 a a2 l c y bp 0.10 0.10 0 to 10 (unit:mm) a a2 a1 e y he c 6.50 4.40 0.20 0.10 6.40 0.10 0.10 1.45 max. 1.15 0.65 0.12 0.10 0.05 0.22 0.05 0.02 0.15 0.50 0.20 11 bp he e d l 3 2 1 note 1.dimensions 1 and 2 2.dimension does not include tr rl78/g12 4. package drawings r01ds0193ej0200 rev.2.00 sep 06, 2013 page 105 of 106 4.2 24-pin products r5f1027aana, r5f10279ana, r5f10278ana, r5f10277ana r5f1037aana, r5f10379ana, r5f10378ana, r5f10377ana r5f1027adna, r5f10279dna, r5f10278dna, r5f10277dna r5f1037adna, r5f10379dna, r5f10378dna, r5f10377dna r5f1027agna, r5f10279gna, r5f10278gna, r5f10277gna r5f1037agna, r5f10379gna, r5f10378gna, r5f10377gna 2012 renesas electronics corporation. all rights reserved. s y e lp sx ba b m a d e 18 12 13 6 7 1 24 a s b a d e a e lp x y 4.00 0.05 0.50 0.05 0.05 4.00 0.05 0.75 0.05 0.40 0.10 s d2 e2 (unit:mm) item dimensions 19 detail of a part exposed die pad item d2 e2 a min nom max 2.45 2.50 exposed die pad variations 2.55 min nom max 2.45 2.50 2.55 b 0.25 0.05 0.07 jeita package code renesas code previous code mass (typ.) [g] p-hwqfn24-4x4-0.50 pwqn0024ke-a p24k8-50-cab-1 0.04 rl78/g12 4. package drawings r01ds0193ej0200 rev.2.00 sep 06, 2013 page 106 of 106 4.3 30-pin products r5f102aaasp, r5f102a9asp, r5f102a8asp, r5f102a7asp r5f103aaasp, r5f103a9asp, r5f103a8asp, r5f103a7asp r5f102aadsp, r5f102a9dsp, r5f102a8dsp, r5f102a7dsp r5f103aadsp, r5f103a9dsp, r5f103a8dsp, r5f103a7dsp r5f102aagsp, r5f102a9gsp, r5f102a8gsp, r5f102a7gsp r5f103aagsp, r5f103a9gsp, r5f103a8gsp, r5f103a7gsp jeita package code renesas code previous code mass (typ.) [g] p-lssop30-0300-0.65 plsp0030jb-b s30mc-65-5a4-3 0.18 s s h j t i g d e f c b k p l u n item b c i l m n a k d e f g h j p 30 16 11 5 a detail of lead end m m t millimeters 0.65 (t.p.) 0.45 max. 0.13 0.5 6.1 0.2 0.10 9.85 0.15 0.17 0.03 0.1 0.05 0.24 1.3 0.1 8.1 0.2 1.2 0.08 0.07 1.0 0.2 3 5 3 0.25 0.6 0.15 u note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. 2012 renesas electronics corporation. all rights reserved. c - 1 revision history rl78/g12 data sheet description rev. date page summary 1.00 dec 10, 2012 - first edition issued 1 modification of 1.1 features 3 modification of 1.2 list of part numbers 4 modification of table 1-1. list of ordering part numbers, note, and caution 7 to 9 modification of package name in 1.4.1 to 1.4.3 14 modification of tables in 1.7 outline of functions 17 modification of description of table in 2.1 absolute maximum ratings (t a = 25c) 18 modification of table, note, and caution in 2.2.1 x1 oscillator characteristics 18 modification of table in 2.2.2 on-chip oscillator characteristics 19 modification of note 3 in 2.3.1 pin characteristics (1/4) 20 modification of note 3 in 2.3.1 pin characteristics (2/4) 23 modification of notes 1 and 2 in (1) 20-, 24-pin products (1/2) 24 modification of notes 1 and 3 in (1) 20-, 24-pin products (2/2) 25 modification of notes 1 and 2 in (2) 30-pin products (1/2) 26 modification of notes 1 and 3 in (2) 30-pin products (2/2) 27 modification of (3) peripheral functions (common to all products) 28 modification of table in 2.4 ac characteristics 29 addition of minimum instruct ion execution time during main system clock operation 30 modification of figures of ac timing test po int and external main system clock timing 31 modification of figure of ac timing test point 31 modification of description and note 2 in (1) during communication at same potential (uart mode) 32 modification of description in (2) during communication at same potential (csi mode) 33 modification of description in (3) during communication at same potential (csi mode) 34 modification of description in (4) during communication at same potential (csi mode) 36 modification of table and note 2 in (5) during communication at same potential (simplified i 2 c mode) 38, 39 modification of table and notes 1 to 9 in (6) communication at different potential (1.8 v, 2.5 v, 3 v) (uart mode) 40 modification of remarks 1 to 3 in (6) communication at different potential (1.8 v, 2.5 v, 3 v) (uart mode) 41 modification of table in (7) communication at different potential (2.5 v, 3 v) (csi mode) 42 modification of caution in (7) communication at different potential (2.5 v, 3 v) (csi mode) 43 modification of table in (8) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (1/3) 44 modification of table and notes 1 and 2 in (8) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (2/3) 45 modification of table, note 1, and caution 1 in (8) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (3/3) 47 modification of table in (9) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) 50 modification of table, note 1, and caution 1 in (10) communication at different potential (1.8 v, 2.5 v, 3 v) (simplified i 2 c mode) 52 modification of remark in 2.5.2 serial interface iica 53 addition of table to 2.6.1 a/d converter characteristics 53 modification of description in 2.6.1 (1) 54 modification of notes 3 to 5 in 2.6.1 (1) 2.00 sep 06, 2013 54 modification of description and notes 2 to 4 in 2.6.1 (2) c - 2 description rev. date page summary 55 modification of description and notes 3 and 4 in 2.6.1 (3) 56 modification of description and notes 3 and 4 in 2.6.1 (4) 57 modification of table in 2.6.2 temperature sensor/internal reference voltage characteristics 57 modification of table and note in 2.6.3 por circuit characteristics 58 modification of table in 2.6.4 lvd circuit characteristics 59 modification of table of lvd detection voltage of interrupt & reset mode 59 modification of number and title to 2.6.5 power supply voltage rising slope characteristics 61 modification of table, figure, and remark in 2.10 timing of entry to flash memory programming modes 62 to 103 addition of products of industrial applications (g: t a = -40 to +105c) 2.00 sep 06, 2013 104 to 106 addition of products of industrial applications (g: t a = -40 to +105c) all trademarks and registered trademarks ar e the property of their respective owners. superflash is a registered trademark of silicon storage technology, inc. in several countries including the united states and japan. caution: this product uses superflash ? technology licensed from silicon storage technology, inc. notes for cmos devices (1) voltage application waveform at input pin: waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between vil (max) and vih (min) due to noise, etc ., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is po ssible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave different ly than bipolar or nmos dev ices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) precaution against esd: a strong electric fi eld, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade t he device operation. steps must be taken to stop generation of static elec tricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequ ate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be gr ounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not necessarily define the in itial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does no t guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the re set signal is received. a reset operation must be ex ecuted immediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the exte rnal power su pply and then the internal power supply. use of the reverse powe r on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the corre ct power on/off sequence must be judged separately for each device and according to related sp ecifications governing the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. t he current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal cu rrent that passes in the device at this time may cause degradation of internal elemen ts. input of signals during the power off state must be judged separately for each device and according to re lated specifications governing the device. notice 1. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 3. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 4. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas electronics product. 5. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". t he recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti-crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat t o human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). you mus t check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas e lectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance desig n. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatib ility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufactu re, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this do cument, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics products, who distributes, disposes of, or othe rwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no responsibility for any losses incurred by yo u or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of renesa s electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. htt p ://www.renesas.co m refer to "htt p ://www.renesas.com/" for the latest and detailed information . r e n esas el ec tr o ni cs am e ri ca in c . 2880 scott boulevard santa clara , ca 95050-2554 , u.s.a . tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-651-700, fax: +44-1628-651-804 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 80 bendemeer road, unit #06-02 hyflux innovation centre singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 renesas electronics mala y sia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petalin g jaya, selan g or darul ehsan, malaysi a tel: +60-3-7955-9390 , fax: +60-3-7955-951 0 renesas electronics korea co. , ltd . 11f., samik lavied' or bld g ., 720-2 yeoksam-don g , kan g nam-ku, seoul 135-080, korea tel: +82-2-558-3737 , fax: +82-2-558-514 1 s ale s o ffi c e s ? 2013 renesas electronics corporation. all ri g hts reserved . colo p hon 2.2 |
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